v1.1
®
IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology
Advanced I/O
Features and Benefits
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
Low Power
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
Mode
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
1
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X , and
1
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
(AGL250 and above)
• I/O Registers on Input, Output, and Enable Paths
‡
• Hot-Swappable and Cold-Sparing I/Os
1
• Programmable Output Slew Rate and Drive Strength
High Capacity
• Weak Pull-Up/-Down
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
Clock Conditioning Circuit (CCC) and PLL1
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Retains Programmed Design When Powered Off
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
In-System Programming (ISP) and Security
Embedded Memory
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• 1 kbit of FlashROM User Nonvolatile Memory
1
®
®
Standard (AES) Decryption (except ARM -enabled IGLOO
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
1
devices) via JTAG (IEEE 1532–compliant)
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
1
®
H•ighFla-PsheLrofcokrmance Routing Hierarchy
to Secure FPGA Contents
A•RMTruPerDoucael-sPsoortrSSRAuMpp(eoxrctepitn×I1G8)LOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
• Segmented, Hierarchical Routing and Clock Structure
IGLOO Product Family
IGLOO Devices
AGL015
AGL030
AGL060 AGL125
AGL250
AGL600
AGL1000
ARM-Enabled IGLOO Devices
System Gates
M1AGL250 M1AGL600
M1AGL1000
15 k
128
384
5
30 k
256
768
5
60 k
512
1,536
10
125 k
1,024
3,072
16
250 k
–
600 k
–
1 M
–
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
6,144
24
13,824
36
24,576
53
–
–
18
36
36
108
24
144
32
–
–
4
8
8
FlashROM Bits
1 k
–
1 k
–
1 k
Yes
1
1 k
Yes
1
1 k
Yes
1
1 k
Yes
1
1 k
Yes
1
4
Secure (AES) ISP
Integrated PLL in CCCs
–
–
1
VersaNet Globals
6
6
18
18
18
18
18
I/O Banks
2
2
2
2
4
4
4
Maximum User I/Os
49
81
96
133
143
235
300
Package Pins
CS
5
3,5
UC81, CS81
QN132
VQ100
CS121
CS196
QN132
VQ100
FG144
CS196
CS281
CS281
3
QFN
QN68
QN132
QN132
VQFP
FBGA
VQ100
VQ100
FG144
3
FG144
FG144,
FG256,
FG484
FG144, FG256,
FG484
Notes:
1. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
2. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze
Technology handbook.
3. Device/package support TBD.
4. AES is not available for ARM-enabled IGLOO devices.
5. The M1AGL250 device does not support this package.
1 AGL015 and AGL030 devices do not support this feature.
‡ Supported only by AGL015 and AGL030 devices.
July 2008
© 2008 Actel Corporation
I