Datasheet > 可编程逻辑 > 现场可编程门阵列> M1AGL1000V5-FCSG281

M1AGL1000V5-FCSG281

更新时间： 2024-02-21 10:24:20

品牌	Logo	应用领域
ACTEL		栅现场可编程门阵列可编程逻辑
页数	文件大小	规格书
216页	6519K
描述
Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 108MHz, 24576-Cell, CMOS, PBGA281, 10 X 10 MM, 1.05 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-281

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技术参数
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M1AGL1000V5-FCSG281 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	10 X 10 MM, 1.05 MM HEIGHT, 0.50 MM PITCH, CSP-281	Reach Compliance Code：	compliant
风险等级：	5.81	Is Samacsys：	N
最大时钟频率：	108 MHz	JESD-30 代码：	S-PBGA-B281
JESD-609代码：	e0	长度：	10 mm
可配置逻辑块数量：	24576	等效关口数量：	1000000
输入次数：	215	逻辑单元数量：	24576
输出次数：	215	端子数量：	281
最高工作温度：	70 °C	最低工作温度：
组织：	24576 CLBS, 1000000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFBGA	封装等效代码：	BGA281,19X19,20
封装形状：	SQUARE	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.05 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	0.5 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

M1AGL1000V5-FCSG281 数据手册

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v1.4

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Features and Benefits

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

†

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X , and

Low Power

†

LVCMOS 2.5 V / 5.0 V Input

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

H^•igh^EasC^ya^Ep^nta^ryci^tt^oy^{/ Exit from Ultra-Low-Power Flash*Freeze Mode}

‡

• Hot-Swappable and Cold-Sparing I/Os

• 15 k to 1 Million System Gates

†

• Programmable Output Slew Rate and Drive Strength

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

Clock Conditioning Circuit (CCC) and PLL^†

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase

Shift, Multiply/Divide,

Delay

• Retains Programmed Design When Powered Off

Capabilities, and External Feedback

In-System Programming (ISP) and Security

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Embedded Memory

Standard (AES) Decryption (except ARM -enabled IGLOO

†

• 1 kbit of FlashROM User Nonvolatile Memory

devices) via JTAG (IEEE 1532–compliant)

†

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

to Secure FPGA Contents

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

A^•RM^TruP^er^Do^uc^ae^l-s^Ps^oo^rtr^SS^RAu^Mpp^(eo^xr^ct^epi^tn^×I¹G⁸⁾LOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

A^•dv^Sa^egn^mce^end^teI^d/O^{, Hierarchical Routing and Clock Structure}

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

IGLOO Product Family

IGLOO Devices

AGL015

AGL030

AGL060 AGL125

AGL250

AGL400

AGL600

AGL1000

ARM-Enabled IGLOO Devices

System Gates

M1AGL250 M1AGL400 M1AGL600 M1AGL1000

15 k

128

384

30 k

256

768

60 k

512

1,536

125 k

1,024

3,072

250 k

2,048

6,144

400 k

–

600 k

–

1 M

–

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

9,216

13,824

24,576

–

108

144

–

FlashROM Bits

1 k

–

1 k

–

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

143

194

235

300

Package Pins

UC/CS

4,5

UC81/CS81

CS121

CS196

CS281

QFN

QN68

QN48, QN68, QN132

QN132

QN132 QN132

VQFP

FBGA

VQ100

FG144

VQ100

FG144

FG144,

FG256,

FG484

FG144,

FG256,

FG484

FG144,

FG256,

FG484

Notes:

1. AES is not available for ARM-enabled IGLOO devices.

2. AGL060 in CS121 does not support the PLL.

3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

4. The M1AGL250 device does not support this package.

5. Device/package support TBD

6. The IGLOOe handbook provides information on higher densities and additional features.

† AGL015 and AGL030 devices do not support this feature.

‡ Supported only by AGL015 and AGL030 devices.

February 2009

12 3 4 5 6 7...216

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