Datasheet > M1020-11I167.2820

M1020-11I167.2820

更新时间： 2024-01-09 03:43:27

品牌	Logo	应用领域
艾迪悌 - IDT		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
10页	423K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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M1020-11I167.2820 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	LCC
包装说明：	QCCN,	针数：	36
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	JESD-30 代码：	S-CQCC-N36
JESD-609代码：	e3	长度：	8.99 mm
功能数量：	1	端子数量：	36
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	3.1 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.635 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	8.99 mm	Base Number Matches：	1

M1020-11I167.2820 数据手册

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M1020/21

Integrated

Circuit

Systems, Inc.

VCSO BASED

CLOCK PLL

P r o d u c t D a t a S h e e t

PLL Operation

Loss of Lock Indicator (LOL) Output Pin

The M1020/21 is a complete clock PLL. It uses a phase

detector and configurable dividers to synchronize the

output of the VCSO with the selected reference clock.

Under normal device operation, when the PLL is locked,

the LOL Phase Detector drives LOL to logic 0. Under

circumstances when the VCSO cannot lock to the input

(as measured by a greater than 4 ns discrepancy

between the feedback and reference clock rising edges

at the LOL Phase Detector) the LOL output goes to logic

1. The LOL pin will return back to logic 0 when the phase

detector error is less than 2 ns. The loss of lock

indicator is a low current LVCMOS output.

The “M” divider divides the VCSO output frequency,

feeding the result into the plus input of the phase

detector.

The output of the “R” divider is fed into the minus input

of the phase detector. The phase detector compares its

two inputs. The phase detector output, filtered

externally, causes the VCSO to increase or decrease in

speed as needed to phase- and frequency-lock the

VCSO to the reference input.

Guidelines for Using LOL

In a given application, the magnitude of peak-to-peak

jitter at the phase detector will usually increase as the R

divider is increased. If the LOL pin will be used to detect

an unusual clock condition, or a clock fault, the

MR_SEL3:0 pins should be set to provide a phase detector

frequency of 5MHz or greater. Otherwise, false LOL

indications may result. A phase detector frequency of

10MHz or greater is desirable when reference jitter is

over 500ps, or when the device is used within a noisy

The value of the M divider directly affects closed loop

bandwidth.

The relationship between the nominal VCSO center

frequency (Fvcso), the M divider, the R divider, and the

input reference frequency (Fin) is:

system environment. Refer to Tables

for phase detector frequency when using the

M1020-11-155.5200 or the M1021-11-155.5200.

3 and 4 on pg. 3

---

Fvcso = Fin ×

For the available M divider and R divider look-up table

combinations, Tables and 4 on pg. 3 list the Total PLL

TriState

Ratio as well as Fin when using the M1020-11-155.5200 or

the M1021-11-155.5200. (See “Ordering Information” on pg.

10.)

The TriState feature puts the LVPECL output driver into

a high impedance state, effectively disconnecting the

driver from the FOUT and nFOUT pins of the device. A

logic 0 is then present on the clock net. The impedance

of the clock net is then set to 50Ωby the external circuit

resistors. (This is in distinction to a CMOS output in

TriState, in which case the net goes to a high

impedance and the logic value floats.) The 50Ω

impedance level of the LVPECL TriState allows

manufacturing In-circuit Test to drive the clock net with

an external 50Ω generator to validate the integrity of

clock net and the clock load.

Post-PLL Divider

The M1020/21 also features a post-PLL (P) divider.

By using the P Divider, the device’s output frequency

(Fout) can be the VCSO center frequency (Fvcso) or

1/2 Fvcso, or 0.

The P_SEL0 and P_SEL1 pins select the value for the P

divider. (See Table 5 on pg. 4.)

When the P divider is included, the complete relation-

ship for the output frequency (Fout) is defined as:

Any unused output (single-ended or differential)

should be left unconnected (floating) in system

application. This minimizes output switching current

and therefore minimizes noise modulation of VCSO.

Fvcso

-----------------

Fout =

= Fin ×

-------------------

R × P

Due to the narrow tuning range of the VCSO

(+200ppm), appropriate selection of all of the following

are required for the PLL be able to lock: VCSO center

frequency, input frequency, and divider selections.

M1020/21 Datasheet Rev 1.0

5 of 10

Revised 28Jul2004

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

1 2 3 456 7 8...10

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