M0564
LIST OF FIGURES
Figure 4.2-1 NuMicro® M0564 Base Series LQFP 48-pin Diagram............................................... 22
Figure 4.2-2 NuMicro® M0564 Base Series LQFP 64-pin Diagram............................................... 23
Figure 4.2-3 NuMicro® M0564 Base Series LQFP 100-pin Diagram............................................. 24
Figure 5.1-1 NuMicro® M0564 Block Diagram ............................................................................... 54
Figure 6.1-1 Functional Block Diagram.......................................................................................... 55
Figure 6.2-1 System Reset Sources .............................................................................................. 58
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 60
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 61
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 62
Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 63
Figure 6.2-6 NuMicro® M0564 Power Mode State Machine .......................................................... 65
Figure 6.2-7 NuMicro® M0564 Power Distribution Diagram........................................................... 68
Figure 6.2-8 SRAM Block Diagram................................................................................................ 71
Figure 6.2-9 SRAM Memory Organization..................................................................................... 72
Figure 6.2-10 UART1_TXD Modulated with PWM Channel.......................................................... 73
Figure 6.2-11 VDET Block Diagram............................................................................................... 74
Figure 6.3-1 Clock Generator Block Diagram................................................................................ 81
Figure 6.3-2 Clock Generator Global View Diagram...................................................................... 82
Figure 6.3-3 System Clock Block Diagram .................................................................................... 83
Figure 6.3-4 HXT Stop Protect Procedure..................................................................................... 84
Figure 6.3-5 SysTick Clock Control Block Diagram....................................................................... 84
Figure 6.3-6 Clock Source of Clock Output ................................................................................... 85
Figure 6.3-7 Clock Output Block Diagram ..................................................................................... 86
Figure 6.20-1 SPI Master Mode Application Block Diagram........................................................ 105
Figure 6.20-2 SPI Slave Mode Application Block Diagram.......................................................... 105
Figure 6.21-1 I2C Bus Timing....................................................................................................... 107
Figure 8.3-1 Typical Crystal Application Circuit ........................................................................... 122
Figure 8.3-2 Typical Crystal Application Circuit ........................................................................... 123
Figure 8.6-1 I2C Timing Diagram ................................................................................................. 132
Figure 8.7-1 SPI Master Mode Timing Diagram .......................................................................... 133
Figure 8.7-2 SPI Slave Mode Timing Diagram ............................................................................ 134
Aug. 20, 2018
Page 6 of 139
Rev 1.01
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