Datasheet > M-ORT8850L1BM680-DB

M-ORT8850L1BM680-DB

更新时间： 2024-09-28 15:43:59

品牌	Logo	应用领域
莱迪思 - LATTICE		栅可编程逻辑
页数	文件大小	规格书
103页	2556K
描述
Field Programmable Gate Array, 624 CLBs, 201000 Gates, 624-Cell, PBGA680, PLASTIC, FBGA-680

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M-ORT8850L1BM680-DB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	PLASTIC, FBGA-680
针数：	680	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	其他特性：	MAXIMUM USABLE GATES 397000
JESD-30 代码：	S-PBGA-B680	JESD-609代码：	e0
长度：	35 mm	湿度敏感等级：	3
可配置逻辑块数量：	624	等效关口数量：	201000
输入次数：	278	逻辑单元数量：	624
输出次数：	278	端子数量：	680
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	624 CLBS, 201000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA680,34X34,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	1.5,1.5/3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	2.51 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	35 mm	Base Number Matches：	1

M-ORT8850L1BM680-DB 数据手册

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ORCA^®ORT8850

Field-Programmable System Chip (FPSC)

Eight-Channel x 850 Mbits/s Backplane Transceiver

November 2002

Data Sheet

Introduction

Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Pro-

grammable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed

a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-

speed serial backplane data transfer. Built on the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC)

architecture, the ORT8850 family is made up of backplane transceivers (SERDES) containing eight channels, each

operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex

synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K

usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-indepen-

dent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for

HDLC for Internet Protocol (IP), designers can build a conﬁgurable interface retaining proven backplane

driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within

a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge

using our PCI soft core.

The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across

a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design

clock domains in a multiboard system, and fewer signals on the backplane. Network designers will beneﬁt from the

backplane transceiver as a network termination device. The backplane transceiver offers SONET scram-

bling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus

the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all

SONET functionality is hidden from the user and no prior networking knowledge is required.

Table 1. ORCA ORT8850 Family – Available FPGA Logic (equivalent to OR4E02 and OR4E06 respectively)

FPGA

System

Gates (K)

PFU

FPGA Max

EBR

Blocks

EBR Bits

(K)

Device

PFU Rows Columns Total PFUs User I/Os

LUTs

4,992

ORT8850L

ORT8850H

624

278

297

201 - 397

471 - 899

2,024

16,192

148

Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate

ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40%

EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage

and 6 PLLs.

www.latticesemi.com

ort8850_01

12 3 4 5 6 7...103

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与M-ORT8850L1BM680-DB相关器件

型号	品牌	获取价格	描述	数据表
M-ORT8850L2BM680-DB	LATTICE	获取价格	Field Programmable Gate Array, 624 CLBs, 201000 Gates, 624-Cell, PBGA680, PLASTIC, FBGA-68
MO-RX3930	ETC	获取价格	FSK RECEIVER MODULE
MO-RX3930-FS	ETC	获取价格	FSK RECEIVER MODULE
MO-RX3930-FS315M	ETC	获取价格	FSK RECEIVER MODULE
MO-RX3930-FS434M	ETC	获取价格	FSK RECEIVER MODULE
MO-RX3930-FS868M	ETC	获取价格	FSK RECEIVER MODULE
MO-RX3930-FS914M	ETC	获取价格	FSK RECEIVER MODULE
MO-RXLC-A	ETC	获取价格	SUPER-REGENERATION RECEIVER MODULE
MO-RXLC-AS315M	ETC	获取价格	SUPER-REGENERATION RECEIVER MODULE
MO-RXLC-AS434M	ETC	获取价格	SUPER-REGENERATION RECEIVER MODULE

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