Datasheet > LY6225616ML-35SLE

LY6225616ML-35SLE

更新时间： 2024-02-12 21:55:08

品牌	Logo	应用领域
台湾来扬 - LYONTEK		静态存储器
页数	文件大小	规格书
14页	194K
描述
SRAM,

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技术参数
数据手册

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LY6225616ML-35SLE 技术参数

生命周期：	Not Recommended	Reach Compliance Code：	compliant
风险等级：	5.8

LY6225616ML-35SLE 数据手册

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LY6225616

256K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.1

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

Dout

tAA

tOH

Previous Data Valid

Data Valid

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

tRC

Address

tAA

CE#

tACE

LB#,UB#

tBA

OE#

tOE

tOH

tOLZ

tBLZ

tCLZ

tOHZ

tBHZ

tCHZ

High-Z

Dout

High-Z

Data Valid

Notes :

1.WE#is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low_.

3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise t_AAis the limiting parameter.

4.t_CLZ, t_BLZ,t_OLZ, t_CHZ,t_BHZand t_OHZare specified with C_L= 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, t_CHZis less than t_CLZ, t_BHZis less than t_BLZ, t_OHZis less than t_OLZ.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

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