Datasheet > LTC3618

LTC3618

更新时间： 2023-12-20 18:46:19

品牌	Logo	应用领域
亚德诺 - ADI		双倍数据速率稳压器
页数	文件大小	规格书
24页	1100K
描述
用于 DDR 终端的双通道、4MHz、±3A、同步降压型稳压器

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

LTC3618 数据手册

LTC3618

Dual 4MHz, 3A

Synchronous Buck Converter

for DDR Termination

FEATURES

DESCRIPTION

The LTC^®3618 is a dual synchronous step-down regulator

using a current mode, constant-frequency architecture. It

provides a complete DDR solution with an input voltage

range from 2.25V to 5.5V.

DDR Power Supply, Termination and Reference

High Efficiency: Up to 94%

Dual Outputs with ±±A Output Current Capability

2.25V to 5.5V Input Voltage Range

±ꢀ% Output Voltage Accuracy

The output of the first step-down regulator offers a high

accuracy V_DDQsupply. A buffered reference generates VTTR

at 50% of VDDQIN and drives loads up to 10mA. The sec-

ond regulator generates the DDR termination voltage (V )

equal to VTTR. Both regulators are capable of deliveri^Tn^Tg

3A of load current at 1MHz switching frequency.

Output Voltage Down to 0.5V

Shutdown Current ≤1µA

VTTR = VDDQIN/2, V = VTTR

FB2

Adjustable Switching Frequency Up to 4MHz

Internal or External Compensation

Selectable 0°/90°/180° Phase Shift Between Channels

Internal or External Soft-Start for V , Internal

Soft-Start for V

Power Good Status Outputs

Low Profile 4mm × 4mm QFN-24 and TSSOP-24

Packages

The operating frequency is externally programmable up to

4MHz, allowing the use of small surface mount inductors.

0°, 90°, or 180° of phase shift between the two chan-

nels can be selected to minimize input current ripple. For

switching noise-sensitive applications, the LTC3618 can

be synchronized to an external clock up to 4MHz.

DDQ

AEC-Q100 Qualified for Automotive Applications

The LTC3618 is offered in leadless 24-pin 4mm × 4mm

QFN and thermally enhanced 24-pin TSSOP packages.

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 5481178, 6498466, 6580258, 6611131.

APPLICATIONS

DDR Memory

Supports DDR, DDR2, and DDR3 Standards

Tracking Supplies

TYPICAL APPLICATION

ꢃ

ꢅꢆ

ꢌ.ꢌꢃ

ꢂꢐꢐꢝꢇ

Efficiency and Power Loss vs Load Current

ꢀꢃ

ꢅꢆ

ꢓꢃ

ꢅꢆꢂ

ꢓꢃ

ꢅꢆꢙ

ꢔꢋꢋ

ꢓꢋ

ꢖꢋ

ꢘꢋ

ꢙꢋ

ꢗꢋ

ꢚꢋ

ꢊꢋ

ꢕꢋ

ꢔꢋ

ꢋ

ꢔꢋ

ꢃDDꢄꢅꢆ

Rꢔꢆꢂ

ꢂꢝꢗ

ꢃ

DDꢄ

ꢜ

ꢞ ꢔ.ꢖꢜ

ꢂ.ꢎꢃꢖꢌꢏ

ꢞꢟꢝꢇ

ꢀꢁꢂ

DDꢝ

ꢊRꢏꢋꢕꢖꢀꢀꢂ

ꢓꢒꢚꢚDꢂ

ꢅꢊꢗꢂ

ꢞꢙꢙꢡ

ꢙꢂꢐꢡ

ꢉꢊꢋꢌꢍꢂꢎ

ꢔ

ꢇꢈꢂ

Rꢊ

ꢜ

ꢇꢇ

ꢞ ꢋ.ꢓꢜ

ꢛꢚDꢘꢖꢀꢜꢆꢋ

ꢓꢗꢏꢀꢘ

ꢃ

ꢊꢊ

ꢌꢠꢙꢡ

ꢀꢁꢙ

ꢇꢈꢙ

ꢐ.ꢠꢃꢖ ꢌꢏ

ꢞꢟꢝꢇ

ꢋ.ꢔ

Rꢔꢆꢙ

ꢓꢒꢚꢚDꢙ

ꢅꢊꢗꢙ

ꢃ

DDꢄ

ꢙ

ꢃ

ꢢ

ꢃꢊꢊR

ꢋ.ꢋꢔ

ꢔꢋ

Rꢘꢇ

ꢀꢒꢆD

ꢓꢒꢆD

ꢋ.ꢋꢔ

ꢋ.ꢔ

ꢔ

ꢐ.ꢐꢂꢝꢇ

ꢌꢍꢂꢎ ꢊꢏꢐꢂꢑ

ꢀꢁꢂD ꢃꢄRRꢅꢆꢇ ꢈꢂꢉ

ꢊꢙꢔꢖ ꢇꢂꢋꢔꢛ

Rev. D

Document Feedback

For more information www.analog.com

12 3 4 5 6 7...24

中文翻译

下载PDF

与LTC3618相关器件

型号	品牌	获取价格	描述	数据表
LTC3618EFE#PBF	Linear	获取价格	LTC3618 - Dual 4MHz, ±3A Synchronous Buck Con
LTC3618EUF#PBF	Linear	获取价格	LTC3618 - Dual 4MHz, ±3A Synchronous Buck Con
LTC3618EUF#TRPBF	Linear	获取价格	LTC3618 - Dual 4MHz, ±3A Synchronous Buck Con
LTC3618IUF#TRPBF	Linear	获取价格	LTC3618 - Dual 4MHz, ±3A Synchronous Buck Con
LTC3619	ADI	获取价格	具平均输入电流限制的 400mA / 800mA 同步降压型 DC/DC 稳压器
LTC3619B	Linear	获取价格	400mA/800mA Synchronous Step-Down DC/DC with Average Input Current Limit
LTC3619B	ADI	获取价格	具平均输入电流限制的 400mA / 800mA 同步降压型 DC/DC 稳压器
LTC3619BEDD-PBF	Linear	获取价格	400mA/800mA Synchronous Step-Down DC/DC with Average Input Current Limit
LTC3619BEDD-TRPBF	Linear	获取价格	400mA/800mA Synchronous Step-Down DC/DC with Average Input Current Limit
LTC3619BEMSE-PBF	Linear	获取价格	400mA/800mA Synchronous Step-Down DC/DC with Average Input Current Limit

与LTC3618相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

8
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

8
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

10
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

11

产品中心

服务支持

精选活动

关于我们

帮助中心

LTC3618

LTC3618 数据手册

与LTC3618相关器件

与LTC3618相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

LTC3618

LTC3618 数据手册

与LTC3618相关器件

与LTC3618相关文章

您还可以找

您在本页遇到什么问题？