LTC2953
PIN FUNCTIONS
GND (Pin 1): Ground.
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of hysteresis. PFI controls the state of the PFO output pin
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and is independent of PB, Vꢁ and UVLO status. Connect
to GND if unused.
VM (Pin 2): Voltage ꢁonitor Input. Input to an accurate
comparator with a 0.5V threshold. Vꢁ controls the state
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PFO (Pin 9): Power Fail Output. This pin is a high voltage
open drain pull-down. PFO pulls low when PFI is below
0.5V. Open circuit when unused.
of the RST output pin and is independent of PB, PFI and
UVLO status. A voltage below 0.5V on this pin asserts
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RST low. Connect to GND if unused.
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KILL (Pin 3): KILL Input. Forcing KILL low releases the
RST (Pin 10): Reset Output. This pin is an open drain
pull-down. Pulls low when Vꢁ input is below 0.5V and is
held low for 200ms after Vꢁ input is above 0.5V. Open
circuit when unused.
enable output. During system turn on, this pin is blanked
by a 512ms internal timer (t
system to pull KILL high. This pin has an accurate 0.6V
threshold and can be used as a power kill voltage monitor.
Set the pin voltage above its threshold if unused.
) to allow the
KILL, ON BLANK
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EN (LTC2953-1, Pin 11): Open Drain Enable Output. This
output is intended to enable system power. EN is asserted
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PDT (Pin 4): Power Down Time Input. A capacitor to
high after a valid PB turn on event (t
). EN is released
DB, ON
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ground determines the additional time (6.4 seconds/μF)
low if: a) KILL is not driven high (by μP) within 512ms of
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that PB or UVLO must be held low before releasing the
the initial valid PB power turn on event, b) KILL is driven
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EN/EN and INT outputs. If this pin is left open, the power
down delay time defaults to 64ms.
lowduringnormaloperation,c)PBorUVLOisassertedand
held low (t > t + t ) during normal operation.
PD, ꢁin
PDT
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EN (LTC2953-2, Pin 11): Open Drain Enable Output. This
PB (Pin 5): Push Button Input. Connecting PB to ground
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output is intended to enable system power. EN is asserted
throughamomentaryswitchprovidesOn/Offcontrolviathe
EN/EN and INT outputs. An internal 100k pull-up resistor
connects to an internal 1.9V bias voltage. The rugged PB
input withstands 10kV ESD HBꢁ and can be pulled up to
27V externally without consuming extra current. Voltages
below ground will not damage the pin.
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low after a valid PB turn on event (t
). EN is released
DB, ON
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high if: a) KILL is not driven high (by μP) within 512ms of
the initial valid PB power turn-on event, b) KILL is driven
lowduringnormaloperation,c)PBorUVLOisassertedand
held low (t > t + t ) during normal operation.
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PD, ꢁin
PDT
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V (Pin 6): Power Supply Input: 2.7V to 27V.
INT (Pin 12): Open Drain Interrupt Output. After a turn off
IN
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) from PB or UVLO, the LTC2953
event is detected (t
DB, OFF
UVLO(Pin7):UVLOComparatorInput.WhenUVLOdrops
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interrupts the system (μP) by asserting INT low. The μP
would perform power down and housekeeping tasks and
below its falling threshold (0.5V) for more than 32ms, the
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LTC2953 asserts INT low, thereby requesting a system
power down. If UVLO remains below its falling threshold
(0.5V) for longer than the adjustable power down delay,
the enable output is released. Additionally, UVLO provides
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thenasserttheKILLpinlow, thusreleasingtheenableout-
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put. The INT pulse width is a minimum of 32ms and stays
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low as long as PB is asserted. If PB is asserted for longer
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+ t , however, the INT and EN/EN outputs
PDT
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than t
PD, ꢁin
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a PB lock out feature that prevents the user from asserting
the enable output when UVLO falls below its threshold.
are immediately released. Open circuit when unused.
Connect to V if unused.
Exposed Pad (Pin 13): Exposed Pad may be left open or
connected to ground.
IN
PFI (Pin 8): Power Fail Comparator Input. Input to an ac-
curate comparator with a 0.5V falling threshold and 4mV
2953f
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