5秒后页面跳转
捷配首页

Datasheet > LTC1669-8CMS8#TR
LTC1669-8CMS8#TR PDF预览

LTC1669-8CMS8#TR

更新时间： 2024-01-05 09:15:38
品牌 Logo 应用领域
凌特 - Linear 光电二极管转换器
页数 文件大小 规格书
16页 149K
描述
LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Package: MSOP; Pins: 8; Temperature Range: 0&deg;C to 70&deg;C

阅读下载

中文翻译

获取价格

LTC1669-8CMS8#TR 技术参数

是否Rohs认证： 不符合生命周期：Active
包装说明：TSSOP, TSSOP8,.19Reach Compliance Code：not_compliant
风险等级：5.63转换器类型：D/A CONVERTER
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
最大线性误差 (EL)：0.24%位数：10
功能数量：1端子数量：8
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.19封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3/5 V
认证状态：Not Qualified子类别：Other Converters
最大压摆率：0.125 mA表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
Base Number Matches：1

LTC1669-8CMS8#TR 数据手册

 浏览型号LTC1669-8CMS8#TR的Datasheet PDF文件第6页浏览型号LTC1669-8CMS8#TR的Datasheet PDF文件第7页浏览型号LTC1669-8CMS8#TR的Datasheet PDF文件第8页浏览型号LTC1669-8CMS8#TR的Datasheet PDF文件第10页浏览型号LTC1669-8CMS8#TR的Datasheet PDF文件第11页浏览型号LTC1669-8CMS8#TR的Datasheet PDF文件第12页 
LTC1669  
APPLICATIONS INFORMATION  
Write Word Protocol Used by the LTC1669  
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address Wr  
A
Command Byte  
A
LSData Byte  
A
MSData Byte  
A
P
1669 TA03  
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition  
Serial Digital Interface  
Write Word Protocol  
The LTC1669 communicates with a host (master) using  
the standard 2-wire interface. The Timing Diagram shows  
the timing relationship of the signals on the bus. The two  
bus lines, SDA and SCL, must be high when the bus is  
not in use. External pull-up resistors or current sources,  
ThemasterinitiatescommunicationwiththeLTC1669with  
aSTARTconditionanda7-bitaddressfollowedbytheWrite  
Bit (Wr) = 0. The LTC1669 acknowledges and the master  
delivers the command byte. The LTC1669 acknowledges  
and latches the command byte into the command byte  
inputregister.Themasterthendeliverstheleastsignificant  
data byte. Again the LTC1669 acknowledges and the data  
is latched into the least significant data byte input register.  
The master then delivers the most significant data byte.  
The LTC1669 acknowledges once more and latches the  
data into the most significant data byte input register.  
Lastly, the master terminates the communication with a  
STOP condition. On the reception of the STOP condition,  
the LTC1669 transfers the input register information to  
output registers and the DAC output is updated.  
2
such as the LTC1694 SMBus/I C Accelerator, are required  
on these lines.  
The LTC1669 is a receive-only (slave) device. The master  
can communicate with the LTC1669 using the Quick Com-  
mand, Send Byte or Write Word protocols as explained  
later.  
The START and STOP Conditions  
When the bus is not in use, both SCL and SDA must be  
high. A bus master signals the beginning of a communica-  
tion to a slave device by transmitting a START condition.  
A START condition is generated by transitioning SDA  
from high to low while SCL is high.  
Slave Address (MSOP Package Only)  
The LTC1669 can respond to one of eight 7-bit addresses.  
The first 4 bits (MSBs) have been factory programmed to  
0100. The first 4 bits of the LTC1669-8 have been factory  
programmed to 0011. The three address bits, AD2, AD1  
and AD0 are programmed by the user and determine the  
LSBs of the slave address, as shown in the table below:  
When the master has finished communicating with the  
slave, it issues a STOP condition. A STOP condition is  
generated by transitioning SDA from low to high while  
SCL is high. The bus is then free for communication with  
2
another I C device.  
LTC1669  
0100 xxx  
0100 000  
0100 001  
0100 010  
0100 011  
0100 100  
0100 101  
0100 110  
0100 111  
LTC-1669-8  
0011 xxx  
0011 000  
0011 001  
0011 010  
0011 011  
0011 100  
0011 101  
0011 110  
0011 111  
AD2  
L
AD1  
L
AD0  
L
Acknowledge  
The Acknowledge signal is used for handshaking between  
the master and the slave. An Acknowledge (active LOW)  
generated by the slave lets the master know that the latest  
byteofinformationwasreceived.TheAcknowledgerelated  
clockpulseisgeneratedbythemaster.Themasterreleases  
the SDA line (HIGH) during the Acknowledge clock pulse.  
The slave-receiver must pull down the SDA line during the  
Acknowledge clock pulse so that it remains a stable LOW  
during the HIGH period of this clock pulse.  
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
1669fa  
9
1...6789101112...16

中文翻译

下载PDF

与LTC1669-8CMS8#TR相关器件

型号 品牌 获取价格 描述 数据表
LTC1669-8IMS8 Linear

获取价格

 		10-Bit Rail-to-Rail Micropower DAC with I2C Interface
LTC1669CMS8 Linear

获取价格

 		10-Bit Rail-to-Rail Micropower DAC with I2C Interface
LTC1669CMS8#PBF Linear

获取价格

 		LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa
LTC1669CMS8#TR Linear

获取价格

 		暂无描述
LTC1669CMS8#TRPBF Linear

获取价格

 		LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa
LTC1669CS5 Linear

获取价格

 		10-Bit Rail-to-Rail Micropower DAC with I2C Interface
LTC1669CS5#TRPBF Linear

获取价格

 		LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa
LTC1669IMS8 Linear

获取价格

 		10-Bit Rail-to-Rail Micropower DAC with I2C Interface
LTC1669IMS8#PBF Linear

获取价格

 		LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa
LTC1669IMS8#TR Linear

获取价格

 		LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Pa

与LTC1669-8CMS8#TR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证