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LTC1669-8CMS8#TR PDF预览

LTC1669-8CMS8#TR

更新时间: 2024-01-25 18:37:39
品牌 Logo 应用领域
凌特 - Linear 光电二极管转换器
页数 文件大小 规格书
16页 149K
描述
LTC1669 - 10-Bit Rail-to-Rail Micropower DAC with I<sup>2</sup>C Interface; Package: MSOP; Pins: 8; Temperature Range: 0&deg;C to 70&deg;C

LTC1669-8CMS8#TR 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:TSSOP, TSSOP8,.19Reach Compliance Code:not_compliant
风险等级:5.63转换器类型:D/A CONVERTER
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
最大线性误差 (EL):0.24%位数:10
功能数量:1端子数量:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3/5 V
认证状态:Not Qualified子类别:Other Converters
最大压摆率:0.125 mA表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

LTC1669-8CMS8#TR 数据手册

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LTC1669  
APPLICATIONS INFORMATION  
Slave Address (SOT-23 Package)  
The Bandgap (BG) bit when set to “0” selects the DAC  
supply voltage as its voltage reference. The full-scale  
output of the DAC with this setting is equal to the supply  
voltage. When the BG bit is set to “1,” the internal bandgap  
reference(≈1.25V)isselectedastheDAC’sreference. The  
full-scale output voltage for this setting is 2.5V.  
The slave address for the SOT-23 package has been  
factory programmed to be “0100 000” (LTC1669) and  
“0100 001” (LTC1669-1). If another address is required,  
please consult the factory.  
Command Byte  
Data Bytes  
7
6
5
4
3
2
1
0
Least Significant Data Byte  
X
X
X
X
X
BG  
SD  
SY  
7
6
5
4
3
2
1
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
SY  
SD  
1
0
Allows update on Acknowledge of SYNC Address only  
Update on Stop condition only (Power-On Default)  
1
0
Puts the device in power-down mode  
Puts the device in standard operating mode  
(Power-On Default)  
Most Significant Data Byte  
7
6
5
4
3
2
1
0
BG  
X
1
0
Selects the internal bandgap reference  
Selects the supply as the reference (Power-On Default)  
X
X
X
X
X
X
D9  
D8  
X = Don’t care  
X
Don’t Care  
Send Byte Protocol  
The stop condition normally initiates the update of the  
DAC’s output latches. Simultaneous update of more than  
one DAC or other devices on the bus can be achieved by  
reissuing new start bit, address, command and data bytes  
before issuing a final stop condition (which will update  
all the devices). An alternate way to achieve simultaneous  
LTC1669 updates is to override the stop condition update  
by setting the “SY” bit of the command byte. Setting this  
bit sets the device to update the DAC output latches only  
at the reception of a SYNC address quick command. The  
actual update occurs on the rising edge of SCL during the  
Acknowledge. In this way, all devices can update on the  
reception of the SYNC address quick command instead  
of the STOP condition.  
The Send Byte protocol used on the LTC1669 is actually a  
subset of the Write Word protocol described previously.  
The Send Byte protocol can only be used to send the  
command byte information to the LTC1669.  
1
7
1
1
8
1
1
S
Slave Address Wr  
A
Command Byte  
A
P
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition  
1669 TA04  
The Send Byte protocol is also used whenever the Write  
Word protocol is interrupted for any reason. Reception of  
a START or STOP condition after the Acknowledge of the  
command byte, but before the Acknowledge of the last  
data byte, will cause both data bytes to be ignored and  
the command byte to be accepted.  
A Shutdown (SD) bit = HIGH will put the device in a low  
powerstatebutretainalldatalatchinformation.Shutdown  
will occur at the reception of a STOP condition. This way  
shutdown could be synchronized to other devices. The  
output impedance of the DAC will go to a high impedance  
state (500kΩ to GND).  
Reception of a START or STOP condition before the Ac-  
knowledgeofthecommandbytewillcausetheinterrupted  
command byte to be ignored.  
1669fa  
10  

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