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LTC1668CG PDF预览

LTC1668CG

更新时间: 2024-02-27 22:12:24
品牌 Logo 应用领域
凌特 - Linear 转换器光电二极管信息通信管理
页数 文件大小 规格书
16页 731K
描述
16-Bit, 50Msps DAC

LTC1668CG 数据手册

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LTC1668  
W W  
U W  
U W  
U
ABSOLUTE AXI U RATI GS  
PACKAGE/ORDER I FOR ATIO  
(Note 1)  
TOP VIEW  
Supply Voltage (VDD)................................................ 6V  
Negative Supply Voltage (VSS) ............................... 6V  
Total Supply Voltage (VDD to VSS) .......................... 12V  
Digital Input Voltage .................... 0.3V to (VDD + 0.3V)  
Analog Output Voltage  
(IOUT A and IOUT B) ........ (VSS – 0.3V) to (VDD + 0.3V)  
Power Dissipation............................................. 500mW  
Operating Temperature Range  
LTC1668C .............................................. 0°C to 70°C  
LTC1668I........................................... 40°C to 85°C  
Storage Temperature Range ................ 65°C to 150°C  
Lead Temperature (Soldering, 10 sec).................. 300°C  
ORDER PART  
NUMBER  
1
2
DB14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
DB13  
DB12  
DB11  
DB10  
DB9  
DB15 (MSB)  
CLK  
LTC1668CG  
LTC1668IG  
3
4
V
DD  
5
DGND  
6
V
DB8  
SS  
7
COMP2  
COMP1  
DB7  
8
DB6  
9
I
DB5  
OUT A  
10  
11  
12  
13  
14  
I
DB4  
OUT B  
LADCOM  
AGND  
DB3  
DB2  
I
DB1  
REFIN  
REFOUT  
DB0 (LSB)  
G PACKAGE  
28-LEAD PLASTIC SSOP  
TJMAX = 110°C, θJA = 100°C/W  
Consult factory for Military grade parts.  
ELECTRICAL CHARACTERISTICS  
The denotes specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = 5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DC Accuracy (Measured at I , Driving a Virtual Ground)  
OUTA  
Resolution  
16  
14  
Bits  
Bits  
Monotonicity  
INL  
Integral Nonlinearity  
Differential Nonlinearity  
Offset Error  
±8  
±4  
LSB  
DNL  
±1  
0.1  
5
LSB  
±0.2  
% FSR  
ppm/°C  
Offset Error Drift  
Gain Error  
GE  
Internal Reference, R  
= 2k  
2
1
% FSR  
% FSR  
IREFIN  
REF  
External Reference, V = 2.5V, R  
= 2k  
IREFIN  
Gain Error Drift  
Internal Reference  
External Reference  
75  
50  
ppm/°C  
ppm/°C  
PSRR  
Power Supply Rejection Ratio  
V
V
= 5V ±5%  
= –5V ±5%  
±0.1  
±0.1  
% FSR/V  
% FSR/V  
DD  
SS  
Analog Output  
I
Full-Scale Output Current  
Output Compliance Range  
1
10  
1
mA  
V
OUTFS  
I
I
= 10mA  
–1  
0.7  
FS  
Output Resistance; R  
Output Capacitance  
, R  
to LADCOM  
1.1  
5
1.5  
kΩ  
pF  
IOUTA IOUTB  
OUTA, B  
Reference Output  
Reference Voltage  
REFOUT Tied to I  
Through 2kΩ  
2.475  
2.5  
25  
6
2.525  
V
ppm/°C  
mV/mA  
REFIN  
Reference Output Drift  
Reference Output Load Regulation  
I
= 0mA to 5mA  
LOAD  
2

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