LTC1265/LTC1265-3.3/LTC1265-5
U
W U U
APPLICATIONS INFORMATION
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1265. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout:
4. Is the Schottky diode closely connected between the
power ground (Pin 12) and switch (Pin 14)?
5. Does the LTC1265 SENSE– (Pin 7) connect to a point
close to RSENSE and the (+) plate of COUT? In adjustable
applications, the resistive divider, R1 and R2, must be
connected between the (+) plate of COUT and signal
ground.
6. AretheSENSE– andSENSE+ leadsroutedtogetherwith
minimum PC trace spacing? The 1000pF capacitor
between Pins 7 and 8 should be as close as possible to
the LTC1265.
1. Are the signal and power grounds segregated? The
LTC1265 signal ground (Pin 11) must return to the (–)
plate of COUT. The power ground (Pin 12) returns to the
anode of the Schottky diode, and the (–) plate of CIN,
whose leads should be as short as possible.
2. Does the (+) plate of the CIN connect to the power VIN
(Pins 1,13) as close as possible? This capacitor pro-
vides the AC current to the internal P-channel MOSFET
and its driver.
7. Is SHDN (Pin 10) actively pulled to ground during
normal operation? The SHDN pin is high impedance
and must not be allowed to float.
3. Is the input decoupling capacitor (0.1µF) connected
closely between power VIN (Pins 1,13) and power
ground (Pin 12)? This capacitor carries the high fre-
quency peak currents.
PWR V
1
2
IN
V
IN
14
13
12
11
10
9
V
IN
SW
D1
PWR V
IN
+
LTC1265
C
IN
0.1µF
3
4
L
PGND
SGND
SHDN
LB
LB
OUT
1k
1000pF
IN
3900pF
5
6
R1
SHDN
C
T
C
OUT
+
I
TH
N/C (V
SENSE
)
FB
R
SENSE
7
8
R2
+
–
SENSE
V
OUT
1000pF
OUTPUT DIVIDER REQUIRED
WITH ADJUSTABLE VERSION ONLY
BOLD LINES INDICATE
HIGH PATH CURRENTS
LTC1265 F05
Figure 5. LTC1265 Layout Diagram (See Board Layout Checklist)
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