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LTC1069-7 PDF预览

LTC1069-7

更新时间: 2023-12-20 18:46:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
10页 163K
描述
线性相位 8 阶低通滤波器

LTC1069-7 数据手册

 浏览型号LTC1069-7的Datasheet PDF文件第3页浏览型号LTC1069-7的Datasheet PDF文件第4页浏览型号LTC1069-7的Datasheet PDF文件第5页浏览型号LTC1069-7的Datasheet PDF文件第7页浏览型号LTC1069-7的Datasheet PDF文件第8页浏览型号LTC1069-7的Datasheet PDF文件第9页 
LTC1069-7  
TYPICAL PERFORMANCE CHARACTERISTICS  
Output Voltage Swing  
vs Temperature  
Supply Current  
Supply Current  
vs Supply Voltage  
vs Clock Frequency  
4.2  
4.1  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
f
= 10Hz  
CLK  
25  
20  
15  
10  
5
85°C  
25°C  
V
= 5V  
S
V
=
5V  
S
4.0  
–40°C  
f
f
= 2.5MHz  
CLK  
CUTOFF  
R
= 100kHz  
= 10k  
L
–4.5  
–4.6  
–4.7  
I
/I  
= 1mA  
SOURCE SINK  
V
= 5V  
S
0
–40  
0
20  
40  
60  
80 100  
0
1
2
3
4
5
6
–20  
0.25  
1.25  
2.25  
3.25  
4.25  
5.25  
SUꢀꢀLY VOLTAGE ( V)  
TEMꢀERATURE (°C)  
CLOCK FREQUENCY (MHz)  
1069-7 G18  
1069-7 G19  
1069-7 G20  
PIN FUNCTIONS  
AGND (Pin 1): Analog Ground. The quality of the analog  
signal ground can affect the filter performance. For either  
single or dual supply operation, an analog ground plane  
surrounding the package is recommended. The analog  
ground plane should be connected to any digital ground  
at a single point. For dual supply operation, ꢀin 1 should  
be connected to the analog ground plane.  
NC (Pins 3, 6): No Connection. ꢀins 3 and 6 are not  
connected to any internal circuitry; they should be tied  
to ground.  
V
(Pin 4): Filter Input. The filter input pin is internally  
IN  
connected to the inverting inputs of two op amps through  
a 36k resistor for each op amp. This parallel combination  
creates an 18k input impedance.  
For single supply operation, ꢀin 1 should be bypassed  
to the analog ground plane with a capacitor 0.47μF or  
larger. An internal resistive divider biases ꢀin 1 to half the  
total power supply. ꢀin 1 should be buffered if used to  
bias other ICs. Figure 1 shows the connections for single  
supply operation.  
ANALOG GROUND  
ꢀLANE  
1
2
3
4
8
7
6
5
AGND  
V
V
OUT  
OUT  
0.47μF  
+
+
V
V
V
LTC1069-7  
0.1μF  
V
NC  
NC  
V
CLK  
IN  
IN  
+
+
V , V (Pins 2, 7): ꢀower Supplies. The V (ꢀin 2) and  
V (ꢀin 7) should be bypassed with a 0.1μF capacitor to  
DIGITAL  
GROUND  
ꢀLANE  
STAR  
SYSTEM  
GROUND  
1k  
an adequate analog ground. The filter’s power supplies  
shouldbeisolatedfromotherdigitalorhighvoltageanalog  
supplies.Alownoiselinearsupplyisrecommended.Using  
switching power supplies will lower the signal-to-noise  
ratio of the filter. Unlike previous monolithic filters, the  
power supplies can be applied in any order, that is, the  
positive supply can be applied before the negative supply  
and vice versa. Figure 2 shows the connections for dual  
supply operation.  
CLOCK  
SOURCE  
1069-7 F01  
Figure 1. Connections for Single Supply Operation  
10697fa  
6

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