LTC1064CN

更新时间： 2024-01-07 20:54:16

品牌	Logo	应用领域
凌特 - Linear		有源滤波器过滤器光电二极管 LTE
页数	文件大小	规格书
16页	389K
描述
Low Noise, Fast, Quad Universal Filter Building Block

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技术参数
数据手册

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LTC1064CN 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	PLASTIC, SOL-24
针数：	24	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.66	有源滤波器类型：	SWITCHED CAPACITOR FILTER
中心频率或截止频率最大范围：	100 kHz	中心频率或截止频率最小范围：	0.0001 kHz
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e0
长度：	15.4 mm	标称负供电电压 (Vsup)：	-8 V
功能数量：	4	端子数量：	24
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
极和零点：	2 AND 0	认证状态：	Not Qualified
响应：	UNIVERSAL	座面最大高度：	2.65 mm
标称供电电压 (Vsup)：	8 V	表面贴装：	YES
技术：	CMOS	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
Base Number Matches：	1

LTC1064CN 数据手册

LTC1064

W U U

APPLICATIONS INFORMATION

ANALOG CONSIDERATIONS

Grounding and Bypassing

Figure2showsanexampleofanidealgroundplanedesign

for a two-sided board. Of course this much ground plane

will not always be possible, but users should strive to get

as close to this as possible. Protoboards are not

recommended.

The LTC1064 should be used with separated analog and

digital ground planes and single point grounding

techniques.

Pin 6 (AGND) should be tied directly to the analog ground

plane.

Buffering the Filter Output

Pin 7 (V⁺) should be bypassed to the ground plane with a

0.1µF ceramic capacitor with leads as short as possible.

Pin 19 (V^–) should be bypassed with a 0.1µF ceramic

capacitor. For single supply applications, V^–can be tied to

the analog ground plane.

For good noise performance, V⁺and V^–must be free of

noise and ripple.

When driving coaxial cables and 1× scope probes, the

filter output should be buffered. This is important espe-

cially when high Qs are used to design a specific filter.

Inadequate buffering may cause errors in noise, distor-

tion, Q and gain measurements. When 10× probes are

used, buffering is usually not required. An inverting buffer

is recommended especially when THD tests are per-

formed. As shown in Figure 3, the buffer should be

adequately bypassed to minimize clock feedthrough.

All analog inputs should be referenced directly to the

single point ground. The clock inputs should be shielded

from and/or routed away from the analog circuitry and a

separate digital ground plane used.

PIN 1 IDENT

FOR BEST HIGH FREQUENCY RESPONSE

PLACE RESISTORS PARALLEL TO DOUBLE-

SIDED COPPER CLAD BOARD AND LAY FLAT

(4 RESISTORS SHOWN HERE TYPICAL)

–7.5V

0.1µF CERAMIC

LTC1064

7.5V

CLOCK

DIGITAL

GROUND

PLANE

0.1µF

CERAMIC

(SINGLE POINT

GROUND)

ANALOG

GROUND

PLANE

NOTE: CONNECT ANALOG AND DIGITAL

GROUND PLANES AT A SINGLE POINT AT

THE BOARD EDGE

1064 F02

Figure 2. Example Ground Plane Breadboard Technique for LTC1064

1...4 5 678 9 10...16

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LTC1064CN#PBF	Linear	Low Noise, Fast, Quad Universal Filter Building Block	获取价格
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LTC1064CN#TRPBF	Linear	IC QUAD SWITCHED CAPACITOR FILTER, RESISTOR PROGRAMMABLE, UNIVERSAL, PDIP24, 0.300 INCH, L	获取价格
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LTC1064CSW	Linear	Low Noise, Fast, Quad Universal Filter Building Block	获取价格
LTC1064CSW#PBF	Linear	LTC1064 - Low Noise, Fast, Quad Universal Filter Building Block; Package: SO; Pins: 24; Te	获取价格

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