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LTC1064-1 PDF预览

LTC1064-1

更新时间： 2023-12-20 18:44:03
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
8页 175K
描述
低噪声、8 阶、时钟可扫频椭圆低通滤波器

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LTC1064-1 数据手册

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LTC1064-1  
U
U
U
PI FU CTIO S (Pin Numbers Refer to the 14-Pin Package)  
operation both pins should be tied to one half supply  
(Figure 2). Also Pin 8 and Pin 10, although they are not  
internally connected should be tied to analog ground or  
system ground. This improves the clock feedthrough  
performance.  
breadboard,useaoneinch,orless,shieldedcoaxialcable;  
the shield should be grounded. In a PC board, use a one  
inch trace or less; surround the trace by a ground plane.  
NC (Pins 8, 10): The “no connection” pins preferably  
should be grounded.  
V+, V– (Pins 4, 12): The V+ and V– pins should be  
bypassed with a 0.1µF capacitor to an adequate analog  
ground. Low noise, nonswitching power supplies are  
recommended. To avoid latchup when the power supplies  
exhibit high turn-on transients, a 1N5817 Schottky diode  
should be added from the V+ and V– pins to ground  
(Figure 1).  
f
CLK (Pin 11): For ±5V supplies the logic threshold level is  
1.4V. For ±8V and 0V to 5V supplies the logic threshold  
levels are 2.2V and 3V respectively. The logic threshold  
levels vary ±100mV over the full military temperature  
range. The recommended duty cycle of the input clock is  
50% although for clock frequencies below 500kHz the  
clock “on” time can be as low as 200ns. The maximum  
clock frequency for ±5V supplies is 4MHz. For ±7V sup-  
plies and above, the maximum clock frequency is 5MHz.  
Donotallowtheclocklevelstoexceedthepowersupplies.  
For clock level shifting (see Figure 3).  
INV A, R(h, I) (Pins 7, 14): A very short connection  
between Pin 14 and Pin 7 is recommended. This connec-  
tion should be preferably done under the IC package. In a  
U
TYPICAL APPLICATIO S  
1
1
14  
14  
R(h, I)  
R(h, I)  
INV C  
INV C  
2
3
4
5
6
7
2
3
4
5
6
7
13  
12  
11  
10  
9
13  
12  
11  
10  
9
V
COMP2*  
V
IN  
V
COMP2*  
V
IN  
IN  
IN  
–
–
–
V
V
AGND  
AGND  
V
LTC1064-1  
LTC1064-1  
0.1µF  
1N5817  
+
+
+
+
V = 15V  
f
0V TO 10V  
f
V
V
V
CLK  
CLK  
0.1µF  
0.1µF  
1N5817  
0.1µF  
NC  
NC  
AGND  
AGND  
5k  
V
V
COMP1*  
INV A  
V
COMP1*  
INV A  
V
OUT  
OUT  
OUT  
OUT  
+
V /2  
8
8
5k  
NC  
NC  
1064 F01  
1064 F02  
Figure 1. Using Schottky Diodes to Protect  
the IC from Power Supply Spikes  
Figure 2. Single Supply Operation. If Fast Power Up  
or Down Transients are Expected, Use a 1N5817  
Schottky Diode Between Pin 4 and Pin 5.  
POWER SOURCE  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
R(h, I)  
+
–
INV C  
V
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
R(h, I)  
INV C  
V
IN  
V
IN  
COMP2*  
+
V
COMP2*  
V
V
IN  
+
IN  
–
V
AGND  
LTC1064-1  
–
0.1µF  
V
AGND  
2.2k  
+
f
V
CLK  
LTC1064-1  
2
0.1µF  
10k  
T L  
+
0.1µF  
f
V
V
CLK  
LEVEL  
NC  
AGND  
1µF  
5k  
10k  
NC  
AGND  
5k  
V
OUT  
COMP1*  
INV A  
–
+
V
COMP1*  
INV A  
V
OUT  
8
OUT  
V
OUT  
NC  
8
5k  
0.1µF  
NC  
1064 F04  
RECOMMENDED OP AMPS:  
LT1022, LT318, LT1056  
0.1µF  
1064 F03  
Figure 3. Level Shifting the Input T2L Clock  
for Single Supply Operation, V+ >6V.  
Figure 4. Buffering the Filter Output. The Buffer Op Amp  
Should Not Share the LTC1064-1 Power Lines.  
10641fa  
5
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