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LS1023ASE8KQA PDF预览

LS1023ASE8KQA

更新时间: 2024-02-06 03:43:11
品牌 Logo 应用领域
恩智浦 - NXP 时钟以太网:16GBASE-TPC
页数 文件大小 规格书
260页 3302K
描述
Multifunction Peripheral, CMOS, PBGA780

LS1023ASE8KQA 技术参数

生命周期:Active包装说明:FBGA,
Reach Compliance Code:unknown风险等级:5.72
其他特性:ALSO OPERATES AT 1V SUPPLY NOM地址总线宽度:14
边界扫描:YES总线兼容性:ETHERNET, I2C, PCI, SATA, SPI, UART, USB
最大时钟频率:1400 MHz外部数据总线宽度:32
JESD-30 代码:S-PBGA-B780长度:23 mm
端子数量:780最高工作温度:105 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装形状:SQUARE
封装形式:GRID ARRAY, FINE PITCH座面最大高度:2.07 mm
最大供电电压:0.93 V最小供电电压:0.87 V
标称供电电压:0.9 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:23 mm
Base Number Matches:1

LS1023ASE8KQA 数据手册

 浏览型号LS1023ASE8KQA的Datasheet PDF文件第2页浏览型号LS1023ASE8KQA的Datasheet PDF文件第3页浏览型号LS1023ASE8KQA的Datasheet PDF文件第4页浏览型号LS1023ASE8KQA的Datasheet PDF文件第5页浏览型号LS1023ASE8KQA的Datasheet PDF文件第6页浏览型号LS1023ASE8KQA的Datasheet PDF文件第7页 
Document Number LS1043A  
Rev. 2, 01/2017  
NXP Semiconductors  
Data Sheet: Technical Data  
LS1043A  
QorIQ LS1043A, LS1023A  
Data Sheet  
Features  
• Four SerDes lanes for high-speed peripheral interfaces  
– Three PCI Express 2.0 controllers supporting x4  
operation  
• LS1043A contains 32-bit /64-bit ARM® Cortex®-A53  
MPCore Processor with the following capabilities:  
– Speed up to 1.6 GHz  
– One Serial ATA (SATA 3.0) controller  
– Up to four SGMII supporting 1000 Mbit/s  
– Up to two SGMII supporting 2500 Mbit/s  
– Up to one XFI (10 GbE) interface  
– Up to one QSGMII  
– 32 KB L1 Instruction Cache w/parity  
– 32 KB L1 Data Cache w/ECC  
– Neon SIMD Co-processor  
– ARM v8 Cryptography Extensions  
– Supports 1000Base-KX  
• 1 MB unified I/D L2 Cache w/ECC  
• Additional peripheral interfaces  
– One Quad Serial Peripheral Interface (QSPI)  
controller, one Deserial Serial Peripheral Interface  
(DSPI) controller  
• Hierarchical interconnect fabric  
– Hardware Managed Data coherency  
– Up to 400 MHz operation  
– Integrated Flash Controller (IFC) supporting NAND  
and NOR flash with 28-bit addressing and 16-bit  
data  
– Three USB 3.0 controllers with integrated PHY  
– Enhanced Secure Digital Host Controller (eSDHC)  
supporting SD 3.0, eMMC 4.4, and eMMC 4.5  
modes  
• One 32-bit DDR3L/DDR4 SDRAM memory controller  
– ECC and interleaving support  
– Up to 1.6 GT/s  
• Data Path Acceleration Architecture (DPAA)  
incorporating acceleration for the following functions:  
– Packet parsing, classification, and distribution  
(FMan)  
– uQE supporting TDM/HDLC  
– Queue management for scheduling, packet  
sequencing, and congestion management (QMan)  
– Hardware buffer management for buffer allocation  
and de-allocation (BMan)  
– Four I2C controllers  
– Two 16550 compliant DUARTs and six low-power  
UARTs (LPUARTs)  
– General Purpose IO (GPIO), eight Flextimers, five  
Watchdog timer, four independent PWM/counters/  
timer  
– Trust Architecture  
– Debug supporting run control, data acquisition,  
high-speed trace, and performance/event monitoring  
– Cryptography acceleration (SEC)  
• Parallel Ethernet interfaces  
– Up to two RGMII interfaces  
– IEEE 1588 support  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  

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