Datasheet > LS1020ASE8KQB

LS1020ASE8KQB

更新时间： 2024-01-18 18:37:06

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
196页	1922K
描述
Layerscape 32-bit Arm Cortex-A7, Dual-core, 1.0GHz, 0 to 105C, Security enabled

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LS1020ASE8KQB 数据手册

Document Number LS1020A

Rev. 3, 05/2016

NXP Semiconductors

Data Sheet: Technical Data

LS1020A

QorIQ LS1020A Data Sheet

Features

• Additional peripheral interfaces

– One high-speed USB 3.0 controller with integrated

PHY

– One high-speed USB 2.0 controller with ULPI

– Enhanced secure digital host controller

(eSDHC/MMC/eMMC)

• ARM® Cortex®-A7 MPCore compliant with ARMv7-

A™ architecture

• LS1020A contains a dual-core Cortex-A7. Each core

includes:

– 32 KB L1 Instruction Cache (ECC protection)

– 32 KB L1 Data Cache (ECC protection)

– NEON Co-processor

– Three I2C controllers

– FlexTimer/PWM

– SPI interface

– Floating Point (FPU)

– QuadSPI controller

– QorIQ Trust Architecture and ARM TrustZone®

– Two DUARTs

– Six LPUART interfaces

– Integrated flash controller supporting NAND and

NOR flash

• Snoop Control Unit (SCU)

• 512 KB unified I/D L2 Cache (ECC protection)

– TDM interface

– Four GPIO controllers supporting up to 109 general

purpose I/O signals

– One 4-channel qDMA controller and one eDMA

controller

• Hierarchical interconnect fabric

– The platform has a single 128-bit AMBA 4 AXI

Coherency Extensions (ACE) master port, which

connects to CCI-400 Interconnect.

• One 8/16/32-bit DDR3L/DDR4 SDRAM memory

controllers

– Global interrupt controller (GIC)

– Thermal monitor unit (TMU)

– ECC and interleaving support

• QUICC Engine ULite block

• VeTSEC Ethernet complex

– 32-bit RISC controller for flexible support of the

communications peripherals

– Up to 3x Gigabit Ethernet

– MII, RMII, RGMII, and SGMII support

– QoS, lossless flow control, and IEEE® 1588

– Serial DMA channel for receive and transmit on all

serial channels

– Two universal communication controllers (TDM

and HDLC) supporting 64 multichannels, each

running at 64 Kbps

• Up to 4 SerDes lanes for high-speed peripheral

interfaces

– Two PCI Express Gen2 controllers

– One Serial ATA 3.0 (SATA 1.5, 3.0, 6.0 Gbps)

controller

• 525 FC-PBGA package, 19 mm x 19 mm

– Two SGMII interfaces supporting 1000 Mbps

• Integrated audio block

– Four synchronous audio interfaces (SAI)

– I2S, AC97, and Codec/DSP interfaces

– Sony/Philips Digital Interconnect Format (S/PDIF)

– Asynchronous Sample Rate Converter (ASRC)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

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