LM555

更新时间： 2024-02-10 09:12:08

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
14页	152K
描述
Single Timer

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技术参数
数据手册

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LM555 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.13
Is Samacsys：	N	模拟集成电路 - 其他类型：	PULSE; RECTANGULAR
JESD-30 代码：	R-PDIP-T8	JESD-609代码：	e0
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5/15 V	认证状态：	Not Qualified
子类别：	Analog Waveform Generation Functions	最大供电电流 (Isup)：	12 mA
最大供电电压 (Vsup)：	18 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	15 V	表面贴装：	NO
技术：	BIPOLAR	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

LM555 数据手册

LM555/NE555/SA555

- –------------------------------------

(R + R )C1

(t) =

= V

1 –

(4)

= C (R + R )In2 = 0.693(R + R )C

(5)

The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:

R_B

V_C1(0-)=2Vcc/3

R_D

+ R

----------------------

C -------------- +

= 0

(6)

(7)

------------------------------------

(R + R )C1

(t) =

Since the duration of the timer output low state(t ) is the amount of time it takes for the V (t) to reach Vcc/3,

------------------------------------

(R + R )C1

(8)

= C (R + R )In2 = 0.693(R + R )C

(9)

Since R is normally R >>R although related to the size of discharging Tr.,

t_L=0.693R C

(10)

B 1

Consequently, if the timer operates in astable, the period is the same with

'T=t +t =0.693(RA+R )C +0.693R C =0.693(R +2R )C ' because the period is the sum of the charge time and discharge

B 1

time. And since frequency is the reciprocal of the period, the following applies.

1.44

frequency,

f = --- = ---------------------------------------

(11)

(R + 2R )C

3. Frequency divider

By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure

8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

1...4 5 678 9 10...14

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