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LF198JAN

更新时间： 2024-01-15 05:48:26
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德州仪器 - TI 采样保持电路
页数 文件大小 规格书
19页 966K
描述
LF198JAN Monolithic Sample-and-Hold Circuits

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LF198JAN 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：SOIC包装说明：CERAMIC, SOIC-14
针数：14Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.24最长采集时间：25 µs
标称采集时间：20 µs放大器类型：SAMPLE AND HOLD CIRCUIT
最大模拟输入电压：11.5 V最小模拟输入电压：-11.5 V
JESD-30 代码：R-CDSO-G14JESD-609代码：e0
湿度敏感等级：1负供电电压上限：-18 V
标称负供电电压 (Vsup)：-15 V功能数量：1
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：SOP封装等效代码：SOP14,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：+-15 V
认证状态：Not Qualified采样并保持/跟踪并保持：SAMPLE
筛选级别：MIL-PRF-38535 Class V座面最大高度：2.58 mm
子类别：Sample and Hold Circuits最大压摆率：6.5 mA
供电电压上限：18 V标称供电电压 (Vsup)：15 V
表面贴装：YES技术：BIPOLAR
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：6.35 mmBase Number Matches：1

LF198JAN 数据手册

 浏览型号LF198JAN的Datasheet PDF文件第4页浏览型号LF198JAN的Datasheet PDF文件第5页浏览型号LF198JAN的Datasheet PDF文件第6页浏览型号LF198JAN的Datasheet PDF文件第8页浏览型号LF198JAN的Datasheet PDF文件第9页浏览型号LF198JAN的Datasheet PDF文件第10页 
AC/DC Parameters (Continued)  
Symbol  
Parameter  
Sub-  
groups  
Conditions  
Notes  
Min Max  
Unit  
%
TROS  
Transient Response  
(overshoot)  
+VCC = 3.5V, -VCC = -26.5V,  
VI = 100mV pulse  
40  
40  
7
7
+VCC = 26.5V, -VCC = -3.5V,  
VI = 100mV pulse  
%
enH  
enS  
Noise  
Noise  
+VCC = 15V, -VCC = -15V  
+VCC = 15V, -VCC = -15V  
10  
10  
mVRMS  
mVRMS  
7
7
DC Parameters: Drift Values  
Delta calculations performed on S-Level devices at group B, subgroup 5 ONLY.  
Symbol  
VIO  
IIB  
Parameters  
Input Offset Voltage  
Input Bias Current  
Conditions  
Sub-  
groups  
Notes  
Min Max  
Unit  
mV  
nA  
+VCC = 15V, -VCC = -15V,  
VCM = 0V  
-0.5  
-2.5  
0.5  
2.5  
1
1
+VCC = 15V, -VCC = -15V,  
VCM = 0V  
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed  
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test  
conditions  
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T  
, θ , and the ambient temperature, T . The maximum  
A
JMAX JA  
allowable power dissipation at any temperature is P = (T  
− T )/θ , or the number given in the Absolute Maximum Ratings, whichever is lower. .  
A JA  
D
JMAX  
Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without  
causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the  
negative supply.  
Note 4: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step  
with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.  
Note 5: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can  
be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range.  
Note 6: See Definition of Terms  
Note 7: Human body model, 100pF discharged through 1.5KΩ  
Typical Performance Characteristics  
Aperture Time  
Dielectric Absorption  
Error in Hold Capacitor  
(Note 6)  
20128117  
20128118  
www.national.com  
6
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