LF198H/NOPB

更新时间： 2024-02-25 23:05:08

品牌	Logo	应用领域
德州仪器 - TI		放大器采样保持电路
页数	文件大小	规格书
15页	564K
描述
单片采样保持电路 \| LMC \| 8 \| -55 to 125

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技术参数
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LF198H/NOPB 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	SOIC	包装说明：	CERAMIC, SOIC-14
针数：	14	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.24	最长采集时间：	25 µs
标称采集时间：	20 µs	放大器类型：	SAMPLE AND HOLD CIRCUIT
最大模拟输入电压：	11.5 V	最小模拟输入电压：	-11.5 V
JESD-30 代码：	R-CDSO-G14	JESD-609代码：	e0
湿度敏感等级：	1	负供电电压上限：	-18 V
标称负供电电压 (Vsup)：	-15 V	功能数量：	1
端子数量：	14	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	SOP	封装等效代码：	SOP14,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	+-15 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
筛选级别：	MIL-PRF-38535 Class V	座面最大高度：	2.58 mm
子类别：	Sample and Hold Circuits	最大压摆率：	6.5 mA
供电电压上限：	18 V	标称供电电压 (Vsup)：	15 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	6.35 mm	Base Number Matches：	1

LF198H/NOPB 数据手册

Logic Input Configurations (Continued)

CMOS

7V ≤ V_LOGIC(Hi State) ≤ 15V

DS005692-35

Threshold = 0.6 (V ) + 1.4V

DS005692-36

Threshold = 0.6 (V ) − 1.4V

Op Amp Drive

DS005692-37

Threshold ≈ +4V

DS005692-38

Threshold = −4V

Application Hints

Hold Capacitor

reduced if the output of the LF198 is digitized quickly after

the hold mode is initiated. The hysteresis relaxation time

constant in polypropylene, for instance, is 10—50 ms. If

A-to-D conversion can be made within 1 ms, hysteresis error

will be reduced by a factor of ten.

Hold step, acquisition time, and droop rate are the major

trade-offs in the selection of a hold capacitor value. Size and

cost may also become important for larger values. Use of the

curves included with this data sheet should be helpful in se-

lecting a reasonable value of capacitance. Keep in mind that

for fast repetition rates or tracking fast signals, the capacitor

drive currents may cause a significant temperature rise in

the LF198.

DC and AC Zeroing

DC zeroing is accomplished by connecting the offset adjust

pin to the wiper of a 1 kΩ potentiometer which has one end

tied to V⁺and the other end tied through a resistor to ground.

The resistor should be selected to give ≈0.6 mA through the

1k potentiometer.

A significant source of error in an accurate sample and hold

circuit is dielectric absorption in the hold capacitor. A mylar

cap, for instance, may “sag back” up to 0.2% after a quick

change in voltage. A long sample time is required before the

circuit can be put back into the hold mode with this type of

capacitor. Dielectrics with very low hysteresis are polysty-

rene, polypropylene, and Teflon. Other types such as mica

and polycarbonate are not nearly as good. The advantage of

polypropylene over polystyrene is that it extends the maxi-

mum ambient temperature from 85˚C to 100˚C. Most ce-

AC zeroing (hold step zeroing) can be obtained by adding an

inverter with the adjustment pot tied input to output. A 10 pF

capacitor from the wiper to the hold capacitor will give 4 mV

hold step adjustment with a 0.01 µF hold capacitor and 5V

logic supply. For larger logic swings, a smaller capacitor

(

10 pF) may be used.

Logic Rise Time

ramic capacitors are unusable with

1% hysteresis. Ce-

ramic “NPO” or “COG” capacitors are now available for

125˚C operation and also have low dielectric absorption. For

more exact data, see the curve Dielectric Absorption Error.

The hysteresis numbers on the curve are final values, taken

after full relaxation. The hysteresis error can be significantly

For proper operation, logic signals into the LF198 must have

a minimum dV/dt of 1.0 V/µs. Slower signals will cause ex-

cessive hold step. If a R/C network is used in front of the

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与LF198H/NOPB相关器件

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LF198JAN-SP	TI	LF198JAN Monolithic Sample-and-Hold Circuits	获取价格

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