Datasheet > L-TTSI002321BL-2-DB

L-TTSI002321BL-2-DB

更新时间： 2024-09-30 02:54:11

品牌	Logo	应用领域
杰尔 - AGERE		/
页数	文件大小	规格书
61页	1017K
描述
2k x 2k Time-Slot Interchanger

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Data Sheet, Revision 3

September 21, 2005

TSI-2

2k x 2k Time-Slot Interchanger

1 Introduction

The last issue of this data sheet was August 31, 2005. A change history is included in Section 11 Change History on page

61. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text

are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or

grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically

mentioned.

This document consists of two major sections:

The TSI-2 device hardware description. This section contains ball information, operating conditions, dc electrical charac-

teristics, timing diagrams, ac characteristics, and packaging information.

The TSI-2 device register description. This section contains register information.

1.1 Related Documents

The documentation package for this device consists of the following documents:

The TSI-2 2k x 2k Time-Slot Interchanger Product Brief, the TSI Family Selection Guide, the TSI-2 2k x 2k Time-Slot

Interchanger Data Sheet (this document), and the TSI-2 Time-Slot Interchanger System Design Guide.

These documents are available on the public website shown below.

If the reader displays this document using Acrobat Reader , clicking on any blue text will bring the reader to that reference

point.

To access related documents, including the documents mentioned above, please go to the following public website, or con-

tact your Agere representative (see the last page of this document).

http://www.agere.com/telecom/time_slot_interchangers.html

1.2 Block Diagram and High-Level Interface Definition

TEST PATTERN

GENERATOR

TEST PATTERN

MONITOR

TEST ACCESS

PORT

2k x 2k Switch Fabric

RECEIVE

CHI

TRANSMIT

CHI

DATA

STORE

MICROPROCESSOR

INTERFACE

WRITE ADDRESS

COUNTER

CONNECTION

STORE

READ ADDRESS

COUNTER

CLOCK

GENERATOR

Figure 1-1. Block Diagram and High-Level Interface Definition

12 3 4 5 6 7...61

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