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KM416V254DT-6 PDF预览

KM416V254DT-6

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管
页数 文件大小 规格书
36页 840K
描述
EDO DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, TSOP2-44/40

KM416V254DT-6 数据手册

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KM416C254D, KM416V254D  
CMOS DRAM  
256K x 16Bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access  
of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time (-5,-6 or -7), power consumption(Normal or  
Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-  
only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode  
DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reli-  
ability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.  
• Extended Data Out Mode operation  
FEATURES  
• 2 CAS Byte/Wrod Read/Write operation  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
• Part Identification  
- KM416C254D/DL (5V, 512 Ref.)  
- KM416V254D/DL (3.3V, 512 Ref.)  
Active Power Dissipation  
Unit : mW  
5V(512 Ref.)  
• Available in 40-pin SOJ 400mil and 44(40)-pin  
packages  
Speed  
-5  
3.3V(512 Ref.)  
-
605  
495  
440  
• Triple +5V±10% power supply (5V product)  
• Triple +3.3V±0.3V power supply (3.3V product)  
-6  
255  
235  
-7  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
VCC  
NO.  
Refresh  
cycle  
Refresh period  
RAS  
UCAS  
LCAS  
W
Normal  
L-ver  
Vcc  
Vss  
Control  
Clocks  
VBB Generator  
C254D  
5V  
512  
8ms  
128ms  
V254D 3.3V  
Lower  
Data in  
Buffer  
DQ0  
to  
Row Decoder  
Refresh Timer  
Refresh Control  
DQ7  
Lower  
Data out  
Buffer  
Performance Range  
Speed  
-5  
Remark  
5V only  
tRAC  
50ns  
60ns  
70ns  
tCAC  
tRC  
tHPC  
Memory Array  
262,144 x16  
Cells  
OE  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Upper  
Data in  
Buffer  
15ns  
84ns  
20ns  
-6  
15ns 104ns 25ns 5V/3.3V  
20ns 124ns 30ns 5V/3.3V  
DQ8  
to  
DQ15  
Upper  
Data out  
Buffer  
-7  
A0~A8  
Column Decoder  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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