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KM416C1200CJ-L5 PDF预览

KM416C1200CJ-L5

更新时间: 2023-06-15 00:00:00
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管
页数 文件大小 规格书
34页 829K
描述
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO42, 0.400 INCH, SOJ-42

KM416C1200CJ-L5 数据手册

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KM416C1000C, KM416C1200C  
KM416V1000C, KM416V1200C  
CMOS DRAM  
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory  
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5 or -6), power con-  
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-  
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This  
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power  
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.  
FEATURES  
• Part Identification  
• Fast Page Mode operation  
• 2 CAS Byte/Word Read/Write operation  
• CAS-before-RAS refresh capability  
- KM416C1000C/C-L (5V, 4K Ref.)  
• RAS-only and Hidden refresh capability  
- KM416C1200C/C-L (5V, 1K Ref.)  
• Self-refresh capability (L-ver only)  
- KM416V1000C/C-L (3.3V, 4K Ref.)  
- KM416V1200C/C-L (3.3V, 1K Ref.)  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
Active Power Dissipation  
Unit : mW  
5V  
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)  
3.3V  
Speed  
400mil packages  
• Single +5V±10% power supply (5V product)  
4K  
1K  
4K  
495  
440  
1K  
-5  
-6  
324  
288  
504  
468  
770  
715  
• Single +3.3V±0.3V power supply (3.3V product)  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
VCC  
Refresh  
cycle  
Refresh period  
RAS  
UCAS  
LCAS  
W
Vcc  
Vss  
NO.  
Control  
Clocks  
Normal  
L-ver  
VBB Generator  
C1000C  
V1000C  
C1200C  
V1200C  
5V  
3.3V  
5V  
4K  
1K  
64ms  
Lower  
128ms  
Data in  
Buffer  
DQ0  
to  
Row Decoder  
Refresh Timer  
Refresh Control  
16ms  
3.3V  
DQ7  
Lower  
Data out  
Buffer  
Memory Array  
1,048,576 x16  
Cells  
OE  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Upper  
Data in  
Buffer  
Perfomance Range  
A0-A11  
(A0 - A9)*1  
A0 - A7  
DQ8  
to  
DQ15  
Speed  
-5  
Remark  
tRAC  
50ns  
60ns  
tCAC  
tRC  
tPC  
Upper  
Data out  
Buffer  
15ns  
90ns  
35ns 5V/3.3V  
Column Decoder  
(A0 - A9)*1  
-6  
15ns 110ns 40ns 5V/3.3V  
Note) *1 : 1K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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