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KK7472

更新时间: 2024-01-07 11:16:21
品牌 Logo 应用领域
可天士 - KODENSHI
页数 文件大小 规格书
5页 324K
描述
AND-Gated J-K Master-Slave Flip- Flops with Reset and Clear

KK7472 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NBase Number Matches:1

KK7472 数据手册

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TECHNICAL DATA  
KK7472  
AND-Gated J-K Master-Slave Flip-  
Flops with Reset and Clear  
LOGIC DIAGRAM  
ORDERING INFORMATION  
KK7472N Plastic  
KK7472D SOIC  
TA = -10° to 70° C for all packages  
PIN ASSIGNMENT  
PIN 14 =VCC  
PIN 7 = GND  
NC - No internal connection  
FUNCTION TABLE  
Inputs  
Output  
Reset Clear Clock  
J
K
X
X
X
L
Q
Q
L
L
H
L
H
L
X
X
X
X
X
X
L
H
L
H*  
Q0  
H
H
L
H*  
Q0  
L
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
H
TOGGLE  
X =don’t care  
Q0 = the level of Q before the indicated input conditions were established.  
TOGGLE: Each output changes to the complement of its previous level on each  
active transition (pulse) of the clock.  
*This configuration is nonstable; that is, it will not persist whenpreset and clear inputs  
return to their inactive (high) level.  
1

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