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KK4541BN PDF预览

KK4541BN

更新时间: 2024-01-23 02:59:55
品牌 Logo 应用领域
可天士 - KODENSHI 模拟波形发生功能信号电路光电二极管
页数 文件大小 规格书
6页 340K
描述
Programmable Timer High-Performance Silicon-Gate CMOS

KK4541BN 技术参数

生命周期:Obsolete包装说明:DIP, DIP14,.3
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NJESD-30 代码:R-PDIP-T14
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:3/18 V认证状态:Not Qualified
子类别:Analog Waveform Generation Functions表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

KK4541BN 数据手册

 浏览型号KK4541BN的Datasheet PDF文件第1页浏览型号KK4541BN的Datasheet PDF文件第3页浏览型号KK4541BN的Datasheet PDF文件第4页浏览型号KK4541BN的Datasheet PDF文件第5页浏览型号KK4541BN的Datasheet PDF文件第6页 
KK4541B  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to +20  
-0.5 to VCC +0.5  
-0.5 to VCC +0.5  
±10  
Unit  
V
VCC  
VIN  
VOUT  
IIN  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
V
V
mA  
mW  
PD  
Power Dissipation in Still Air, Plastic DIP+  
SOIC Package+  
750  
500  
PD  
Tstg  
TL  
Power Dissipation per Output Transistor  
Storage Temperature  
100  
-65 to +150  
260  
mW  
°C  
Lead Temperature, 1 mm from Case for 10 Seconds  
(Plastic DIP or SOIC Package)  
°C  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C  
SOIC Package: : - 7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
Min  
3.0  
0
Max  
18  
Unit  
V
DC Supply Voltage (Referenced to GND)  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
VIN, VOUT  
TA  
VCC  
+125  
V
-55  
°C  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.  
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this  
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or  
V
OUT)VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused  
outputs must be left open.  
2

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