ISL8130
Pin Descriptions(Continued)
PIN #
QFN, QSOP
SYMBOL
SGND
I/O
DESCRIPTION
8, 15
This pin provides the signal ground for the IC. Tie this pin to the ground plane through the lowest impedance
connection.
9, 16
RT
I
This is the oscillator frequency selection pin. Connecting this pin directly to VCC5 will select the oscillator free
running frequency of 300kHz. By placing a resistor from this pin to GND, the oscillator frequency can be
programmed from 100kHz to 1.4MHz. Figure 2 shows the oscillator frequency vs RT resistance.
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
150
RT (kΩ)
FIGURE 2. OSCILLATOR FREQUENCY vs RT
10, 17
FB
I
This pin is connected to the feedback resistor divider and provides the voltage feedback signal for the
controller. This pin sets the output voltage of the converter.
11, 18
12, 19
COMP
ENSS
I/O
I
This pin is the error amplifier output pin. It is used as the compensation point for the PWM error amplifier.
This pin provides enable/disable function and soft-start for the PWM output. The output drivers are turned
off when this pin is held below 1V.
13, 20
14, 1
15, 2
PGOOD
CDEL
O
I
This pin provides a power-good status. It is an open collector output used to indicate the status of the output
voltage.
The PGOOD signal can be delayed by a time proportional to a CDEL current of 2µA and the value of the
capacitor connected between this pin and ground. A 0.1µF will typically provide 125ms delay.
PGND
This pin provides the power ground for the IC. Tie this pin to the ground plane through the lowest impedance
connection.
16, 3
17, 4
LGATE
PVCC
O
O
This pin provides the PWM-controlled gate drive for the lower MOSFET in Buck and Buck-Boost configuration.
This pin is the power connection for the gate drivers. Connect this pin to the VCC5 pin. Connect a minimum
of 1.0µF ceramic decoupling capacitor as close to the IC as possible at this pin.
18, 5
PHASE
This pin also provides a return path for the upper gate driver. In a Buck configuration, it is the junction point
of the inductor, the upper MOSFET source, and the lower MOSFET drain. For Boost, SEPIC, and Flyback
configurations, this pin is tied to the power ground.
19, 6
20, 7
UGATE
BOOT
This pin provides the PWM-controlled gate drive for the main switching MOSFET in all configurations.
This pin is used to generate level-shifted gate drive signals on the UGATE pin. Connect this pin to the junction
of the bootstrap capacitor and the cathode of the bootstrap diode in a Buck or Buck-Boost configuration. For
other topologies, connect this pin to PVCC. Please refer to typical application circuits beginning on page 5 for
details.
21 (QSOP only)
EP
This pad is electrically isolated. Connect this pad to the signal ground plane using at least five vias for a
robust thermal conduction path.
FN7954 Rev.4.00
Mar 24, 2017
Page 3 of 23
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