ISL8126
Functional Pin Descriptions(Continued)
PIN
NUMBER
SYMBOL
DESCRIPTION
29, 13
VSEN1+, VSEN2+
These pins are the positive inputs of the standard unity gain operational amplifier for differential remote
sense for the corresponding channel (Channels 1 and 2), and should be connected to the positive rail of the
load. These pins can also provide precision output voltage trimming capability by pulling a resistor from
this pin to the positive rail of the load (trimming down) or the return (typical VSEN1-, VSEN2- pins) of the
load (trimming up). By setting the resistor divider connected from the output voltage to the input of the
differential amplifier, the desired output voltage can be programmed. To minimize the system accuracy
error introduced by the input impedance of the differential amplifier, a resistor below 1kΩ is recommended
to be used for the lower leg (ROS) of the feedback resistor divider.
The typical input impedance of VSEN+ with respect to VSEN- is 500kΩ. With VSEN2- pulled within 400mV
of VCC, the corresponding error amplifier is disabled and VSEN2+ is one of the two pins to determine the
relative phase relationship between the internal clock of both channels and the CLKOUT signal. See Table 1
on page 23 for details.
28, 14
ISEN1B, ISEN2B
These pins are the inverting (-) inputs of the current sensing amplifiers to provide r
, DCR, or precision
resistor current sensing together with the ISEN1A, ISEN2A pins. Refer to “2-Phase Operation with rDS(ON)
DS(ON)
Sensing” on page 9 for r
DCR sensing set up.
sensing set up and “2-Phase Operation with DCR Sensing” on page 8 for
DS(ON)
27, 15
16
ISEN1A, ISEN2A
VIN
These pins are the non-inverting (+) inputs of the current sensing amplifiers to provide r
precision resistor current sensing together with the ISEN1B, ISEN2B pins.
, DCR, or
DS(ON)
This pin is the input of the internal linear regulator. It should be tied directly to the input rail. The internal
linear device is protected against reverse bias generated by the remaining charge of the decoupling
capacitor at PVCC when losing the input rail. When used with an external 3.3V to 5V supply, this pin can be
tied directly to PVCC to bypass the internal LDO.
25, 17
24, 18
23, 19
BOOT1, BOOT2
UGATE1, UGATE2
PHASE1, PHASE2
These pins provide the bootstrap biases for the high-side drivers. Internal bootstrap diodes connected to
the PVCC pin provide the necessary bootstrap charge. Its typical operational voltage range is 2.5V to 5.6V.
These pins provide the gate signals to drive the high-side devices and should be connected to the MOSFETs’
gates.
Connect these pins to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. These
pins represent the return path for the high-side gate drives.
22, 20
21
LGATE1, LGATE2
PVCC
These pins provide the drive for the low-side devices and should be connected to the MOSFETs’ gates.
This pin is the output of the internal series linear regulator. It provides the bias for both low-side and
high-side drives. Its operational voltage range is 3V to 5.6V. A 10µF ceramic capacitor is required for
decoupling PVCC to ground.
26
VCC
This pin provides bias power for the analog circuitry. An RC filter is recommended between the connection
of this pin to a 3V to 5.6V bias (typically PVCC). R is suggested to be a 5Ω resistor. And in 3.3V applications,
the R could be shorted to allow the low end input in concerns of the VCC falling threshold. The VCC
decoupling capacitor is strongly recommended to be a low ESR ceramic capacitor. This pin can be powered
either by the internal linear regulator or by an external voltage source.
EPAD
GND
The bottom pad is the signal and power ground plane. All voltage levels are referenced to this pad. This pad
provides a return path for the low-side MOSFET drives and internal power circuitries as well as all analog
signals. Connect this pad to the circuit ground with the shortest possible path (more than 5 to 6 vias to the
internal ground plane, placed on the soldering pad are recommended).
Ordering Information
PART NUMBER
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(Notes 1, 2, 3)
PART MARKING
ISL8126CRZ
ISL8126 CRZ
ISL8126 IRZ
0 to +70
32 Ld 5x5 QFN
32 Ld 5x5 QFN
L32.5x5B
L32.5x5B
ISL8126IRZ
ISL8126EVAL1Z
NOTES:
-40 to +85
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8126. For more information on MSL please see techbrief TB363.
FN7892 Rev.2.00
January 29, 2015
Page 5 of 39
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