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ISL6559CBZ PDF预览

ISL6559CBZ

更新时间: 2024-02-15 11:48:40
品牌 Logo 应用领域
瑞萨 - RENESAS 开关光电二极管
页数 文件大小 规格书
21页 1044K
描述
Multiphase PWM Controller; SOIC28; Temp Range: 0° to 70°

ISL6559CBZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP28,.4
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.73模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE控制技术:PULSE WIDTH MODULATION
最大输入电压:5.25 V最小输入电压:4.75 V
标称输入电压:5 VJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:17.9 mm
湿度敏感等级:3功能数量:1
端子数量:28最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Switching Regulator or Controllers
表面贴装:YES切换器配置:PHASE-SHIFT
最大切换频率:1000 kHz温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

ISL6559CBZ 数据手册

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DATASHEET  
ISL6559  
Multi-Phase PWM Controller  
FN9084  
Rev 8.00  
December 29, 2004  
The ISL6559 provides core-voltage regulation by driving 2 to  
4 interleaved synchronous-rectified buck-converter channels  
in parallel. Interleaving the channel timing results in  
increased ripple frequency which reduces input and output  
ripple currents. The reduction in ripple results in lower  
component cost, reduced dissipation, and a smaller  
implementation area.  
Features  
• Multi-Phase Power Conversion  
- 2, 3 or 4 Phase Operation  
• Active Channel Current Balancing  
• Precision r  
DS(ON)  
- Lossless  
- Low Cost  
Current Sharing  
The ISL6559 uses cost and space-saving r  
sensing  
• Input Voltage: 12V or 5V Bias  
• Precision CORE Voltage Regulation  
- ±1% System Accuracy Over Temperature  
- Differential Remote Output Voltage Sensing  
- Programmable Reference Offset  
• Microprocessor Voltage Identification Input  
- 5-Bit VID Input  
DS(ON)  
for channel current balance, active voltage positioning, and  
over-current protection. Output voltage is monitored by an  
internal differential remote sense amplifier. A high-bandwidth  
error amplifier drives the output voltage to match the  
programmed 5-bit DAC reference voltage. The resulting  
compensation signal guides the creation of pulse width  
modulated (PWM) signals to control companion Intersil  
MOSFET drivers. The OFS pin allows direct offset of the  
DAC voltage from 0V to 50mV using a single external  
resistor. The entire system is trimmed to ensure a system  
accuracy of ±1% over temperature.  
- 0.800V to 1.550V in 25mV Steps  
- Dynamic VID Technology  
• Programmable Droop Voltage  
• Fast Transient Recovery Time  
• Over Current Protection  
Outstanding features of this controller IC include  
Dynamic VIDTM technology allowing seamless on-the-fly VID  
changing without the need of any external components.  
Output voltage “droop” or active voltage positioning is  
optional. When employed, it allows the reduction in size and  
cost of the output capacitors required to support load  
transients. A threshold-sensitive enable input allows the use  
of an external resistor divider for start-up coordination with  
Intersil MOSFET drivers or any other devices powered from  
a separate supply.  
• Digital Soft Start  
• Threshold Sensitive Enable Input  
• High Ripple Frequency (160kHz to 4MHz)  
• QFN Package:  
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat  
No Leads - Package Outline  
- Near Chip Scale Package footprint, which improves PCB  
efficiency and has a thinner profile  
Pb-Free Available (RoHS Compliant)  
Applications  
Superior over-voltage protection is achieved by gating on the  
lower MOSFET of all phases to crowbar the output voltage.  
• AMD Hammer Family Processor Voltage Regulator  
• Low Output Voltage, High Current DC-DC Converters  
• Voltage Regulator Modules  
An optional second crowbar on V , formed with an external  
IN  
MOSFET or SCR gated by the OVP pin, is triggered when  
an over-voltage condition is detected. Under-voltage  
conditions are detected, but PWM operation is not disrupted.  
Over-current conditions cause a hiccup-mode response as  
the controller repeatedly tries to restart. After a set number  
of failed startup attempts, the controller latches off. A power  
good logic signal indicates when the converter output is  
between the UV and OV thresholds.  
Pinouts  
ISL6559CB (28 LEAD SOIC)  
ISL6559CR (32 LEAD QFN)  
TOP VIEW  
TOP VIEW  
GND  
OVP  
1
2
3
4
5
6
7
8
9
28 EN  
27 FS/DIS  
26 PGOOD  
25 PWM4  
24 ISEN4  
23 ISEN1  
22 PWM1  
21 PWM2  
20 GND  
VID4  
VID3  
VID2  
VID1  
VID0  
OFS  
32 31 30 29 28 27 26 25  
VID2  
VID1  
VID0  
NC  
1
2
3
4
5
6
7
8
24 PWM4  
23 ISEN4  
22 ISEN1  
21 PWM1  
20 PWM2  
19 GND  
OFS  
COMP  
COMP  
FB  
FB 10  
IOUT 11  
19 ISEN2  
18 ISEN3  
17 PWM3  
16 VCC  
18 ISEN2  
17 ISEN3  
NC  
VDIFF 12  
VSEN 13  
RGND 14  
9
10 11 12 13 14 15 16  
15 GND  
NC = NO CONNECT  
FN9084 Rev 8.00  
December 29, 2004  
Page 1 of 21  

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