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ISL5314_05

更新时间: 2024-02-25 13:38:50
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
16页 292K
描述
Direct Digital Synthesizer

ISL5314_05 数据手册

 浏览型号ISL5314_05的Datasheet PDF文件第2页浏览型号ISL5314_05的Datasheet PDF文件第3页浏览型号ISL5314_05的Datasheet PDF文件第4页浏览型号ISL5314_05的Datasheet PDF文件第5页浏览型号ISL5314_05的Datasheet PDF文件第6页浏览型号ISL5314_05的Datasheet PDF文件第7页 
ISL5314  
®
Data Sheet  
July 28, 2005  
FN4901.2  
Direct Digital Synthesizer  
Features  
The 14-bit ISL5314 provides a complete Direct Digital  
Synthesizer (DDS) system in a single 48-pin LQFP package.  
A 48-bit Programmable Carrier NCO (numerically controlled  
oscillator) and a high speed 14-bit DAC (digital to analog  
converter) are integrated into a stand alone DDS.  
• 125MSPS output sample rate with 5V digital supply  
• 100MSPS output sample rate with 3.3V digital supply  
• 14-bit digital-to-analog (DAC) with internal reference  
• Parallel control interface for fast tuning (50MSPS control  
register write rate) and serial control interface  
The DDS accepts 48-bit center and offset frequency control  
information via a parallel processor interface. A 40-bit  
frequency tuning word can also be loaded via an asynchronous  
serial interface. Modulation control is provided by 3 external  
pins. The PH0 and PH1 pins select phase offsets of 0, 90,  
180 and 270 degrees, while the ENOFR pin enables or zeros  
the offset frequency word to the phase accumulator.  
• 48-bit programmable frequency control  
• Offset frequency register and enable pin for fast FSK  
• Small 48-pin LQFP packaging  
Pb-Free plus anneal available (RoHS compliant)  
Applications  
The parallel processor interface has an 8-bit write-only data  
input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe  
(WR), and a Write Enable (WE). The processor can update  
all registers simultaneously by loading a set of master  
registers, then transfer all master registers to the slave  
registers by asserting the UPDATE pin.  
• Programmable local oscillator  
• FSK, PSK modulation  
• Direct digital synthesis  
• Clock generation  
Ordering Information  
Pinout  
PART #  
TEMP. RANGE (°C) PACKAGE PKG. DWG. #  
48-PIN LQFP (Q48.7X7A)  
ISL5314IN  
-40 to 85  
-40 to 85  
48 LQFP  
Q48.7x7A  
Q48.7x7A  
TOP VIEW  
ISL5314INZ  
(See Note)  
48 LQFP  
(Pb-free)  
ISL5314EVAL2  
25  
Evaluation Board  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material  
sets; molding compounds/die attach materials and 100% matte tin plate  
termination finish, which are RoHS compliant and compatible with both SnPb  
and Pb-free soldering operations. Intersil Pb-free products are MSL classified  
at Pb-free peak reflow temperatures that meet or exceed the Pb-free  
requirements of IPC/JEDEC J STD-020.  
48 47 46 45 44 43 42 41 40 39 3837  
A2  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
C2  
A3  
C1  
C0  
ENOFR  
DGND  
CLK  
2
3
PH0  
PH1  
SSYNC  
DVDD  
4
5
Block Diagram  
6
7
ISL5314  
SCLK  
DVDD  
DGND  
DGND  
RESET  
8
9
C(7:0)  
UPDATE  
COMPOUT  
SDATA  
DVDD  
DGND  
A(3:0)  
10  
PHASE  
REFLO  
REFIO  
11  
12  
ACCUM.  
WR  
WE  
IN-  
-
13 14 15 16 17 18 19 20 21 22 23 24  
+
IN+  
UPDATE  
COMP1  
COMP2  
SDATA  
SSYNC  
SCLK  
SINE  
WAVE  
ROM  
14 BIT  
DAC  
IOUTA  
IOUTB  
ENOFR  
PH(1:0)  
INT  
REF  
REFIO  
REFLO  
RESET  
CLK  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  

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