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ISB35389

更新时间: 2024-02-08 08:04:25
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
15页 347K
描述
HCMOS STRUCTURED ARRAY

ISB35389 数据手册

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ISB35000 SERIES  
HCMOS STRUCTURED ARRAY  
PRELIMINARY DATA  
FEATURES  
Fully independent power and ground  
configurations for inputs, core and outputs.  
0.5 micron triple layer metal HCMOS process  
featuring retrograde well technology, low  
resistance salicided active areas, polysilicide  
gates and thin metal oxide.  
Programmable I/O ring capability up to 1000  
pads.  
Output buffers capable of driving ISA, EISA,  
PCI, MCA, and SCSI interface levels.  
3.3 V optimized transistor with 5 V I/O interface  
capability  
Active pull up and pull down devices.  
Buskeeper I/O functions.  
2 - input NAND delay of 0.210 ns (typ) with  
fanout = 2.  
Oscillators for wide frequency spectrum.  
Broad range of 400 SSI cells.  
Broad I/O functionality including LVCMOS,  
LVTTL, GTL, PECL, and LVDS.  
300 element macrofunction library.  
Design For Test includes LSSD macro library  
option and IEEE 1149.1 JTAG Boundary Scan  
architecture built in.  
High drive I/O; capability of sinking up to 48 mA  
with slew rate control, current spike suppression  
and impedance matching.  
Cadence and Mentor based design system with  
interfaces from multiple workstations.  
Metallised generators to support SPRAM and  
DPRAM, plus an extensive embedded function  
library.  
Broad ceramic and plastic package range.  
Combines Standard Cell Features with Sea of  
Gates time to market.  
Latchup trigger current +/- 500 mA.  
ESD protection +/- 4000 volts.  
Table 1. Product range  
Internal  
Device Name  
Estimated 2  
Gates  
Total Usable3  
Gates  
Maximum4  
Device Pads  
Maximum5  
I/O  
Total Sites1  
ISB35083  
ISB35130  
ISB35166  
ISB35208  
ISB35279  
ISB35389  
ISB35484  
ISB35666  
ISB35832  
124,416  
194,400  
249,696  
311,904  
418,176  
584,064  
726,624  
998,784  
1,247,616  
82,944  
129,600  
166,464  
207,936  
278,784  
389,376  
484,416  
665,856  
831,744  
58,060  
90,720  
188  
232  
260  
288  
332  
388  
432  
504  
560  
172  
216  
244  
272  
316  
372  
416  
488  
544  
116,524  
145,555  
195,148  
253,094  
314,870  
399,513  
499,046  
Notes : 1. Internal sites is based on the number of placement sites available to the route and place software  
2. A factor of 1.5 is used to derive the gate complexity from the total available sites. This number is in Nand2 equivalents  
3. Factors of 70%, 65%, and 60% have been used to calculate the routing efficiency. This number may vary depending on the  
design.  
4. 16 corner pads are dedicated to internal and external power supplies. I/O pads may be configured for additional power.  
5. Maximum I/O = total device pads minus power pads.  
May 1994  
1/15  

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