wordsꢀbyꢀ32ꢀbits.
36ꢀbits.ꢀTheꢀIS61LPS102432Bꢀisꢀorganizedꢀasꢀ1,048,476ꢀ
TheꢀIS61LPS/VPS204818Bꢀisꢀorganizedꢀ
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
1M x 36, 1M x 32, 2M x 18
36 Mb SYNCHRONOUS PIPELINED,
SINgLE CYCLE DESELECT STATIC RAM
NOVEMBER 2017
FEATURES
DESCRIPTION
Theꢀ36Mbꢀproductꢀfamilyꢀfeaturesꢀ high-speed,ꢀlow-powerꢀ
synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀburstable,ꢀ
high-performanceꢀ memoryꢀ forꢀ communicationꢀ andꢀ net-
workingꢀapplications.ꢀTheꢀIS61LPS/VPS102436Bꢀandꢀ
IS64LPS102436Bꢀareꢀorganizedꢀasꢀ1,048,476ꢀwordsꢀbyꢀ
•ꢀ Internalꢀself-timedꢀwriteꢀcycle
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ
control
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ
asꢀ2,096,952ꢀwordsꢀbyꢀ18ꢀbits.ꢀFabricatedꢀwithꢀISSI'sꢀ
advancedꢀ CMOSꢀ technology,ꢀ theꢀ deviceꢀ integratesꢀ aꢀ
2-bitꢀburstꢀcounter,ꢀhigh-speedꢀSRAMꢀcore,ꢀandꢀhigh-
driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀmonolithicꢀcircuit.ꢀAllꢀ
synchronousꢀinputsꢀpassꢀthroughꢀregistersꢀcontrolledꢀbyꢀ
aꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.
•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-
pansionꢀandꢀaddressꢀpipelining
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs
•ꢀ AutoꢀPower-downꢀduringꢀdeselect
•ꢀ Singleꢀcycleꢀdeselect
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ
oneꢀtoꢀfourꢀbytesꢀwideꢀasꢀcontrolledꢀbyꢀtheꢀwriteꢀcontrolꢀ
inputs.
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackage
•ꢀ PowerꢀSupply
Separateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀwritten.ꢀ
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ
writeꢀenableꢀ(BWE)ꢀinputꢀcombinedꢀwithꢀoneꢀorꢀmoreꢀ
individualꢀbyteꢀwriteꢀsignalsꢀ(BWx). Inꢀaddition,ꢀGlobalꢀ
Writeꢀ(GW)ꢀisꢀavailableꢀforꢀwritingꢀallꢀbytesꢀatꢀoneꢀtime,ꢀ
regardlessꢀofꢀtheꢀbyteꢀwriteꢀcontrols.
ꢀ LPS:ꢀVdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)
VPS:ꢀVdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)
VVPS:ꢀVdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
•ꢀ JEDECꢀ100-PinꢀQFP,ꢀ119-ballꢀBGA,ꢀandꢀ165-
ballꢀBGAꢀpackages
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSPꢀ(AddressꢀStatusꢀ
Processor)ꢀorꢀADSCꢀ(AddressꢀStatusꢀCacheꢀController)ꢀ
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-
atedꢀinternallyꢀandꢀcontrolledꢀbyꢀtheꢀADVꢀ(burstꢀaddressꢀ
advance)ꢀinputꢀpin.ꢀ
•ꢀ Lead-freeꢀavailable
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ
orꢀleftꢀfloating.
FAST ACCESS TIME
Symbol
tkq
Parameter
250
2.8
4
200
3.1
5
166
Units
ns
Clock Access Time
Cycle Time
3.8
6
tkc
ns
Frequency
250
200
166
MHz
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. C
11/03/2017
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