Datasheet > INT201

INT201

更新时间： 2024-02-09 13:10:07

品牌	Logo	应用领域
帕沃英蒂格盛 - POWERINT		驱动器
页数	文件大小	规格书
12页	104K
描述
High-side Driver IC

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技术参数
数据手册

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INT201 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
高边驱动器：	YES	输入特性：	SCHMITT TRIGGER
接口集成电路类型：	BUFFER OR INVERTER BASED MOSFET DRIVER	JESD-30 代码：	R-PDSO-G8
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	TOTEM-POLE	标称输出峰值电流：	0.3 A
输出极性：	INVERTED	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
最大压摆率：	3 mA	最大供电电压：	16 V
最小供电电压：	10 V	标称供电电压：	15 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子位置：	DUAL
断开时间：	0.6 µs	接通时间：	1.5 µs
Base Number Matches：	1

INT201 数据手册

INT201

HV+

PHASE 2

INT201

PHASE 1

PHASE 3

INT200

3-PHASE

BRUSHLESS

DC MOTOR

HS IN

LS IN

HV-

PI-1467-042695

Figure 4. Using the INT200 and INT201 in a 3-phase Configuration.

General Circuit Operation

One phase of a three-phase brushless

DCmotordrivecircuitisshowninFigure

4 to illustrate an application of the

INT200/201. The LS IN signal directly

controlsMOSFETQ1. TheHS INsignal

causes the INT200 to command the

INT201toturnMOSFETQ2onoroffas

required. The INT200 will ignore input

signals that would command both Q1

and Q2 to conduct simultaneously,

protecting against shorting the HV+ bus

to HV-.

The INT201 is latched on and off by the

edges of the appropriate low-side logic

signal (HS INfor the INT200 andHS IN

for the INT202). The high-side driver

willlatchoffandstayoffifthebootstrap

capacitor discharges below the

undervoltage lockout threshold.

Undervoltage lockout-induced turn off

can occur during conditions such as

powerrampup,motorstart,orlowspeed

operation.

vs. ON TIME

BOOTSTRAP

1000

100

Local bypassing for the low-side driver

isprovidedbyC1. Bootstrapbiasforthe

high-side driver is provided by D1 and

C2. Slew rate and effects of parasitic

oscillations in the load waveforms are

controlled by resistors R1 and R2.

= 100 nC

= 20 nC

0.1

Theinputsaredesignedtobecompatible

with 5 V CMOS logic levels and should

notbeconnectedtoV_DD. NormalCMOS

power supply sequencing should be

observed. Theorderofsignalapplication

should be V_DD, logic signals, and then

HV+.

0.01

0.1

High Side ON Time (ms)

Figure 5. High-side On Time versus Bootstrap Capacitor.

100

2/96

1 234 5 6 7...12

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