APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation.
V–
V+
Applications with noisy or high-impedance power-supply lines
may require decoupling capacitors close to the device pins.
4
7
380kΩ
380kΩ
380kΩ
The output voltage is equal to the differential input volt-
age between pins 2 and 3. The common mode input
voltage is rejected.
2
3
V2
6
Internal circuitry connected to the compensation pin 8 can-
cels the parasitic distributed capacitance between the feed-
back resistor, R2, and the IC substrate. For specified dy-
namic performance, pin 8 should be grounded or connected
through a 0.1µF capacitor to an AC ground such as V+.
VO = V3 – V2
V3
21.1kΩ
20kΩ
+15V
8
1
5
100kΩ
–15V
+15V
50kΩ
±1.5mV
Range
–15V
(a)
10Ω
1µF
Tantalum
1µF
Tantalum
4
R1
7
R2
380kΩ
V–
V+
380kΩ
2
3
4
7
–In = V2
380kΩ
380kΩ
R3
2
3
6
380kΩ
V2
VO = V3 – V2
+In = V3
6
380kΩ
R5
R4
20kΩ
V
= V – V
O
3
2
21.1kΩ
V3
8
1
5
V+
21.1kΩ
20kΩ
100µA
1/2 REF200
8
1
5
FIGURE 1. Basic Power and Signal Connections.
100Ω
100Ω
COMMON-MODE REJECTION
±10mV
OPA27
(b)
Common-mode rejection (CMR) of the INA117 is depend-
ent on the input resistor network, which is laser-trimmed for
accurate ratio matching. To maintain high CMR, it is impor-
tant to have low source impedances driving the two inputs.
A 75Ω resistance in series with pin 2 or 3 will decrease CMR
from 86dB to 72dB.
10kΩ
Offset adjustment is regulated—
insensitive to power supply variations.
100µA
1/2 REF200
Resistance in series with the reference pins will also degrade
CMR. A 4Ω resistance in series with pin 1 or 5 will decrease
CMRR from 86dB to 72dB.
V–
Most applications do not require trimming. Figures 2 and 3
show optional circuits that may be used for trimming offset
voltage and common-mode rejection.
FIGURE 2. Offset Voltage Trim Circuits.
Some applications, however, apply voltages to the reference
terminals (pins 1 and 5). A more complete transfer function
is:
TRANSFER FUNCTION
Most applications use the INA117 as a simple unity-gain
difference amplifier. The transfer function is:
VO = V3 – V2 + 19 • V5 – 18 • V1
V5 and V1 are the voltages at pins 5 and 1.
VO = V3 – V2
V3 and V2 are the voltages at pins 3 and 2.
INA117
6
SBOS154A