Datasheet > IMSH1GU03A1F1C-16J

IMSH1GU03A1F1C-16J

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
奇梦达 - QIMONDA		动态存储器双倍数据速率
页数	文件大小	规格书
49页	986K
描述
DDR DRAM Module, 128MX64, CMOS, GREEN, UDIMM-240

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Advance Internet Data Sheet

IMSH[1G/2G][U/E]x3A1F1C(T)

DDR3 Unbuffered DIMM

TABLE 2

Performance Table for DDR3–1066 and DDR3–800

QAG Speed Code

Module Speed Bin

Device Speed Bin

CL-n_RCD-n_RP

–10F

–10G

–08D

–08E

Unit

Note

PC3

–8500F

–1066F

7-7-7

–8500G

–1066G

8-8-8

–6400D

–800D

5-5-5

–6400E

–800E

6-6-6

DDR3

CL and CWL settings for maximum

clock frequency

CL = 7

CWL = 6

CL = 8

CWL = 6

CL = 5

CWL = 5

CL = 6

CWL = 5

MHz

Maximum Clock Frequency

and Data Rate

533

1066

533

1066

400

800

400

800

MHz

Mb/s

with above CL and CWL settings

Minimum Clock Frequency

and Data Rate

400

800

400

800

300

600

300

600

MHz

Mb/s

with above CL and CWL settings

1) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also

minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting. For details, refer to Chapter 4.1 Speed Bins.

Rev. 0.63, 2008-08

03052008-R2G5-2FN2

1 2 345 6 7...49

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