Datasheet > IMP705CUA

IMP705CUA

更新时间： 2024-01-09 21:41:15

品牌	Logo	应用领域
IMP		监控
页数	文件大小	规格书
9页	167K
描述
LOW-POWER レP SUPERVISOR CIRCUITS

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IMP705CUA 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP8,.25	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.91	Is Samacsys：	N
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	1.2/5 V
认证状态：	Not Qualified	子类别：	Power Management Circuits
最大供电电流 (Isup)：	0.14 mA	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

IMP705CUA 数据手册

IMP705/6/7/8, 813L

Detail Descriptions

RESET/RESET Operation

Manual Reset (MR)

The RESET/RESET signals are designed to start a µP/µC in a The active-LOW manual reset input is pulled high by a 250µA

known state or return the system to a known state.

pull-up current and can be driven low by CMOS/TTL logic or a

mechanical switch to ground. An external debounce circuit is

unnecessary since the 140ms minimum reset time will debounce

mechanical pushbutton switches.

The IMP707/708 have two RESET outputs, one active-HIGH

RESET and one active-LOW RESET output. The IMP813L has

only an active-HIGH output. RESET is simply the complement

of RESET.

By connecting the watchdog output (WDO) and MR, a watchdog

timeout forces RESET to be generated. The IMP813L should be

used when an active-HIGH RESET is required.

RESET is guaranteed to be LOW with V above 1.2V. During a

power-up sequence, RESET remains low until the supply rises

above the threshold level, either 4.65V, 4.40V or 4.00V. RESET goes

high approximately 200ms after crossing the threshold.

Watchdog Timer

The watchdog timer available on the IMP705/706/813L monitors

µP/µC activity. If activity is not detected within 1.6 seconds, the

internal timer puts the watchdog output, WDO, into a LOW

state. WDO will remain LOW until activity is detected at WDI.

During power-down, RESET goes LOW as V falls below the

threshold level and is guaranteed to be under 0.4V with V

above 1.2V.

In a brownout situation where V falls below the threshold

level, RESET pulses low. If a brownout occurs during an already-

initiated reset, the pulse will continue for a minimum of 140ms.

The watchdog function is disabled, meaning it is cleared and not

counting, if WDI is floated or connected to a three-stated circuit.

The watchdog timer is also disabled if RESET is asserted. When

RESET becomes inactive and the WDI input sees a high or low

transition as short as 50ns, the watchdog timer will begin a 1.6

Auxiliary Comparator

All devices have an auxiliary comparator with 1.25V trip point second countdown. Additional transitions at WDI will reset the

and uncommitted output (PFO) and noninverting input (PFI). watchdog timer and initiate a new countdown sequence.

This comparator can be used as a supply voltage monitor with an

WDO will also become LOW and remain so, whenever the

external resistor voltage divider. The attenuated voltage at PFI

supply voltage, V_CC, falls below the device threshold level. WDO

should be set just below the 1.25 threshold. As the supply level

goes HIGH as soon as V_CCtransitions above the threshold. There

falls, PFI is reduced causing the PFO output to transit LOW.

is no minimum pulse width for WDO as there is for the RESET

Normally PFO interrupts the processor so the system can be shut

outputs. If WDI is floated, WDO essentially acts as a low-power

down in a controlled manner.

output indicator.

v_RT

WDI

t_RS

t_WD

t_WP

RESET

WDO

t_WD

MR extermally

set low

RESET

RESET triggered by MR

t_RS

t_MD

t_MR

(RESET)

IMP813L

WDO

705_05.eps

705_04.eps

Figure 1. WDI Three-state operation

Figure 2. Watchdog Timing

1999 IMP, Inc.

408-432-9100/www.impweb.com

1 2 3 456 7 8 9

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