Datasheet > IMP1232LP

IMP1232LP

更新时间： 2024-01-05 02:19:32

品牌	Logo	应用领域
IMP		光电二极管
页数	文件大小	规格书
7页	106K
描述
5V レP Power Suppl er Supply Monit y Monitor and or and Reset Cir eset Circuit

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技术参数
数据手册

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IMP1232LP 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.71
Is Samacsys：	N	Base Number Matches：	1

IMP1232LP 数据手册

IMP1232LP/LPS

Application Information

Watchdog Timer and ST Input

A watchdog timer stops and restarts a microprocessor that is A HIGH-to-LOW ST signal transition must be regularly issued

“hung-up”. Through the time delay input, TD, three watchdog no later than the minimum time-out period defined by the state of

time-out periods are selectable: 150ms, 610ms and 1,200ms. If the the TD signal. This guarantees the watchdog timer does not

strobe input, ST, is not strobed LOW prior to timeout, reset signals time-out.

become active. On power-up or after the supply voltage returns to

Timeouts periods of approximately 150ms, 610ms or 1,200ms are

an in-tolerance condition, the reset signal remains active for

selected through the TD pin.

250ms minimum, allowing the power supply and system micro-

processor to stabilize.

Watchdog Time-Out Period (ms)

TD Voltage Level

ST Pulses as short as 20ns can be detected.

Min

62.5

250

500

Nominal

150

Max

250

Valid

Strobe

Valid

Strobe

Invalid

Strobe

GND

Floating

610

1000

2000

1200

1232_t03.eps

t_ST

t_TD

The watchdog timer cannot be disabled. It must be strobed with a

high-to-low transition to avoid a watchdog timeout.

t_RST

t_TD

(Max)

(Min)

RESET

1232_09.eps

Note: ST is ignored whenever a reset is active.

Figure 5. Timing Diagram: Strobe Input

IMP1232LP/LPS

MREQ

PBRST

V_CC

10kΩ

µP

RESET

Address

Bus

Decoder

TOL

RESET

GND RESET

1232_07.eps

Figure 6. Application Circuit: Watchdog Timer

1999 IMP, Inc.

408-432-9100/ www.impweb.com

1 2 3 456 7

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