IMP1232LP/LPS
Absolute Maximum Ratings
Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V
Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . –0.5V to VCC + 0.5V
Voltage on PBRST, RESET, RESET . . . . . . . . –0.5V to VCC + 0.5V
Operating Temperature Range . . . . . . . . . . . –40°C to 85°C
(N/ EMA version)
Soldering Temperature . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to 125°C
0°C to 70°C
Voltages measured with respect to ground.
These are stress ratings only and functional operation is not implied.
Electrical Characteristics
Unless otherwise stated, 4.5V ≤ VCC ≤ 5.5V and over the operating temperature range of 0°C to +70°C (–40°C to +85°C for N/ EMA
devices). All voltages are referenced to ground.
Parameter
Supply Voltage (VCC
Symbol
VCC
VIH
Conditions
Min
4.5
Typ
Max
5.5
Units
V
)
ST and PBRST Input High Level
ST and PBRST Input Low Level
VCC Trip Point (TOL = GND)
2
VCC + 0.3V
0.8
V
VIL
–0.3
4.50
4.25
62.5
500
250
V
VCCTP
VCCTP
tTD
4.62
4.37
150
4.74
V
VCC Trip Point (TOL = VCC
)
4.49
V
Watchdog Time-Out Period
Watchdog Time-Out Period
Watchdog Time-Out Period
Output Voltage
TD = GND
250
ms
ms
ms
V
tTD
TD = VCC
1200
610
2000
1000
tTD
TD floating
VOH
IOH
I = –500µA, Note 3
Output = 2.4V , Note 2
Output = 0.4V,
Note 1
VCC - 0.5V VCC - 0.1V
Output Current
– 8
10
–10
mA
mA
µA
V
Output Current
IOL
Input Leakage
IIL
–1.0
1.0
0.4
RESET Low Level
VOL
Internal Pull-Up Resistor
Operating Current (CMOS)
Input Capacitance
Note 1
40
kΩ
µA
pF
pF
ms
ICC1
CIN
30
5
Output Capacitance
COUT
tPB
10
PBRST Manual Reset
Minimum Low Time
PBRST = VIL
Note 4
20
Reset Active Time
ST Pulse Width
tRST
tST
250
20
610
5
1000
8
ms
ns
µs
VCC Fail Detect to
RESET or RESET
tRPD
VCC Slew Rate
tF
4.75V to 4.25V
300
µs
PBRST Stable LOW to
tPDLY
20
ms
RESET and RESET Active
V
CC Detect to RESET or
RESET Inactive
CC Slew Rate
tRPU
tR
tRISE = 5µs
250
0
610
1000
ms
ns
V
4.25V to 4.75V
Notes: 1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down
until VCC falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be
strobed.
©
1999 IMP, Inc.
408-432-9100/ www.impweb.com
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