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IM1P-67202AV-45 PDF预览

IM1P-67202AV-45

更新时间: 2024-02-24 20:32:52
品牌 Logo 应用领域
TEMIC 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
17页 180K
描述
FIFO, 1KX9, 45ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

IM1P-67202AV-45 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.7最长访问时间:45 ns
周期时间:55 nsJESD-30 代码:R-GDIP-T28
内存密度:9216 bit内存宽度:9
功能数量:1端子数量:28
字数:1024 words字数代码:1000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1KX9
输出特性:3-STATE可输出:NO
封装主体材料:CERAMIC, GLASS-SEALED封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子位置:DUALBase Number Matches:1

IM1P-67202AV-45 数据手册

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M67201A/M67202A  
512 9 & 1 K 9 CMOS Parallel FIFO  
Introduction  
The M67201A/202A implement a first-in first-out Using an array of eigh transistors (8 T) memory cell and  
algorithm, featuring asynchronous read/write operations. fabricated with the state of the art 1.0 µm lithography  
The FULL and EMPTY flags prevent data overflow and named SCMOS, the M 67201A/202A combine an  
underflow. The Expansion logic allows unlimited extremely low standby supply current (typ = 1.0  
µA) with  
expansion in word size and depth with no timing fast access time at 25 ns over the full temperature range.  
a
penalties. Twin address pointers automatically generate All versions offer battery backup data retention capability  
internal read and write addresses, and no external address with a typical power consumption at less than 5 µW.  
information are required for the TEMIC FIFOs. Address  
pointers are automatically incremented with the write pin  
For military/space applications that demand superior  
levels  
of  
performance  
and  
reliability  
the  
and read pin. The 9 bits wide data are used in data  
communications applications where a parity bit for error  
checking is necessary. The Retransmit pin reset the Read  
pointer to zero without affecting the write pointer. This is  
very useful for retransmitting data when an error is  
detected in the system.  
M 67201A/202A is processed according to the methods  
of the latest revision of the MIL STD 883 (class B or S)  
and/or ESA SCC 9000.  
Features  
D First-in first-out dual port memory  
D 512 × 9 organisation (M 67201A)  
D 1024 × 9 organisation (M 67202A)  
D Fast access time  
D Asynchronous read/write operations  
D Empty, full and half flags in single device mode  
D Retransmit capability  
D Bi-directional applications  
20*, 25, 35, 45, 55 ns, commercial, industrial and  
automotive  
D Battery back-up operation : 2 V data retention  
D TTL compatible  
20*, 25, 30, 40, 50 ns, military  
D Wide temperature range :  
D Single 5 V ± 10 % Power Supply (1)  
D High performance SCMOS technology  
– 55°C to + 125°C  
(1) 3.3 V versions are also available. Please consult sales.  
D 67201AL/202AL low power 67201AV/202AV very low  
power  
D Fully expandable by word width or depth  
* Preview. Please Consult Sales.  
MATRA MHS  
1
Rev. D (11 April. 97)  

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