ICS87951I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
FEATURES
GENERAL DESCRIPTION
• Fully integrated PLL
The ICS87951I is a low voltage, low skew 1-to-9
Differential-to-LVCMOS/LVTTL Cock Generator
and a member of the HiPerClockS™ family of High
• 9 single ended 3.3V LVCMOS/LVTTLoutputs
HiPerClockS™
Performance Clock Solutions from ICS. The • Selectable single ended CLK0 or differential
ICS87951I has two selectable clock inputs. The
CLK1, nCLK1 inputs
single ended clock input accepts LVCMOS or LVTTL input
levels. The CLK1, nCLK1 pair can accept most standard differ-
ential input levels. With output frequencies up to 180MHz, the
ICS87951I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87951I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with “zero delay”.
• The single ended CLK0 input can accept the following
input levels: LVCMOS or LVTTL input levels
• CLK1, nCLK1 supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Output frequency range: 25MHz to 180MHz
• VCO range: 200MHz to 480MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 375ps (maximum)
• PLL reference zero delay: 350ps window (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC951
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
VDDA
EXT_FB
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QC0
VDDO
QC1
GND
QD0
VDDO
QD1
GND
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
ICS87951I
CLK1
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
87951AYI
www.icst.com/products/hiperclocks.html
REV. B JULY 10, 2003
1