5秒后页面跳转
IDTQS5LV931-80Q8 PDF预览

IDTQS5LV931-80Q8

更新时间: 2024-09-30 14:51:31
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 49K
描述
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20

IDTQS5LV931-80Q8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QSOP包装说明:QSOP-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N输入调节:SCHMITT TRIGGER
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:8.65 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:6最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.3 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9116 mm
最小 fmax:80 MHzBase Number Matches:1

IDTQS5LV931-80Q8 数据手册

 浏览型号IDTQS5LV931-80Q8的Datasheet PDF文件第2页浏览型号IDTQS5LV931-80Q8的Datasheet PDF文件第3页浏览型号IDTQS5LV931-80Q8的Datasheet PDF文件第4页浏览型号IDTQS5LV931-80Q8的Datasheet PDF文件第5页浏览型号IDTQS5LV931-80Q8的Datasheet PDF文件第6页浏览型号IDTQS5LV931-80Q8的Datasheet PDF文件第7页 
QS5LV931  
3.3V Low Skew CMOS  
PLL Clock Driver With  
Integrated Loop Filter  
Q
Q
UALITY  
S
EMICONDUCTOR, NC.  
I
FEATURES/BENEFITS  
DESCRIPTION  
• JEDEC LVTTL compatible level  
• Clock input is 5V tolerant  
• Q outputs, Q/2 output  
• < 300ps output skew, Q0-Q4  
• Outputs 3-state and reset while OE/RST low  
• PLL disable feature for low frequency testing  
• Internal loop filter RC network  
• Internal VCO/2 option  
• Balanced drive outputs ± 24mA  
• 80MHz maximum frequency  
• Industrial temperature range  
• Available in space saving QSOP package  
The QS5LV931 Clock Driver uses an internal phase  
locked loop (PLL) to lock low skew outputs to a  
reference clock input. Six outputs are available:  
Q0-Q4, Q/2. Careful layout and design ensure  
< 300ps skew between the Q0-Q4, and Q/2 outputs.  
The QS5LV931 includes an internal RC filter which  
provides excellent jitter characteristics and eliminates  
the need for external components. Various combina-  
tions of feedback and a divide-by-2 in the VCO path  
allow applications to be customized for linear VCO  
operation over a wide range of input SYNC frequen-  
cies. The PLL can also be disabled by the PLL_EN  
signal to allow low frequency or DC testing. The  
QS5LV931 is designed for use in cost sensitive high-  
performancecomputingsystems,workstations,multi-  
board computers, networking hardware, and main-  
frame systems. Several can be used in parallel or  
scattered throughout a system for guaranteed low  
skew, system-wide clock distribution networks. In the  
QSOP package, the QS5LV931 clock driver repre-  
sents the best value in small form factor, high-perfor-  
mance clock management products.  
For more information on PLL clock driver products,  
see Application Note AN-22A.  
Figure 1. Functional Block Diagram  
FEEDBACK  
PLL_EN  
FREQ_SEL  
SYNC  
0
1
1
0
OE/RST  
PHASE  
DETECTOR  
LOOP  
FILTER  
VCO  
/2  
R
D
R
D
R
D
R
D
R
D
R
Q
D
Q
Q
Q
Q
Q
Q
Q/2  
Q4  
Q3  
Q2  
Q1  
Q0  
MDSC-00022-00  
QUALITY SEMICONDUCTOR, INC.  
1
DECEMBER 15, 1997  

与IDTQS5LV931-80Q8相关器件

型号 品牌 获取价格 描述 数据表
IDTQS74153ATQ IDT

获取价格

HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
IDTQS74153ATSO IDT

获取价格

HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
IDTQS74153CTQ IDT

获取价格

HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
IDTQS74153CTSO IDT

获取价格

HIGH-SPEED CMOS DUAL 4-INPUT MULTIPLEXER
IDTQS74253ATQ ETC

获取价格

4-Input Digital Multiplexer
IDTQS74253ATS1 ETC

获取价格

4-Input Digital Multiplexer
IDTQS74253ATSO ETC

获取价格

4-Input Digital Multiplexer
IDTQS742827ATQ IDT

获取价格

HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFER
IDTQS742827ATSO IDT

获取价格

HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFER
IDTQS742827BTQ IDT

获取价格

HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFER