IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
VIRTUAL
PHYSICAL
0xffffffff
Kernel Mapped
(kseg2)
Any
0xc0000000
0xa0000000
0x80000000
Kernel Uncached
(kseg1)
Physical
Memory
3548MB
Kernel Cached
(kseg0)
User Mapped
Cacheable
(kuseg)
Any
Memory
512MB
0x00000000
2874 drw 03
Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions
The base versions of the architecture (the IDT79R3051
When using the base versions of the architecture, the
and IDT79R3052) remove the TLB and institute a fixed system designer can implement a distinction between the
address mapping for the various segments of the virtual user tasks and the kernel tasks, without having to execute
address space. The base processors support distinct kernel page management software. This distinction can take the
andusermodeoperationwithoutrequiringpagemanagement form of physical memory protection, accomplished by ad-
software, leading to a simpler software model. The memory dress decoding, or in other forms. In systems which do not
mapping used by these devices is illustrated in Figure 4. Note wish to implement memory protection, and wish to have the
that the reserved address spaces shown are for compatibility kernel and user tasks operate out of a single unified memory
with future family members; in the current family members, space, upper address lines can be ignored by the address
references to these addresses are translated in the same decoder, and thus all references will be seen in the lower
fashion as their respective segments, with no traps or excep- gigabyte of the physical address space.
tions taken.
VIRTUAL
PHYSICAL
0xffffffff
1MB Kernel Rsvd
Kernel Cacheable
Tasks
1024MB
2048MB
Kernel Cached
(kseg2)
0xc0000000
0xa0000000
0x80000000
Kernel Uncached
(kseg1)
Kernel/User
Cacheable
Tasks
Kernel Cached
(kseg0)
1MB User Rsvd
User
Cached
(kuseg)
Inaccessible
512MB
512MB
Kernel Boot
and I/O
0x00000000
2874 drw 04
Figure 4. Virtual-to-Physical Mapping of Base Architecture Versions
5.3
3