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IDT72V235L20TF8 PDF预览

IDT72V235L20TF8

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
25页 247K
描述
FIFO, 2KX18, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64

IDT72V235L20TF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, STQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.62
最长访问时间:12 ns其他特性:EASILY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):50 MHz周期时间:20 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:36864 bit
内存集成电路类型:OTHER FIFO内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:10 mm
Base Number Matches:1

IDT72V235L20TF8 数据手册

 浏览型号IDT72V235L20TF8的Datasheet PDF文件第17页浏览型号IDT72V235L20TF8的Datasheet PDF文件第18页浏览型号IDT72V235L20TF8的Datasheet PDF文件第19页浏览型号IDT72V235L20TF8的Datasheet PDF文件第21页浏览型号IDT72V235L20TF8的Datasheet PDF文件第22页浏览型号IDT72V235L20TF8的Datasheet PDF文件第23页 
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
NO WRITE  
NO WRITE  
2
1
WCLK  
D0 - D17  
FF  
1
2
(1)  
tSKEW1  
(1)  
tSKEW1  
tDS  
tDS  
DATA WRITE  
Wd  
tWFF  
tWFF  
tWFF  
WEN  
RCLK  
tENH  
tENH  
tENS  
tENS  
REN  
OE  
LOW  
tA  
tA  
DATA IN OUTPUT REGISTER  
NEXT DATA READ  
DATA READ  
Q0 - Q17  
4294 drw 24  
NOTES:  
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising  
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.  
2. LD = HIGH.  
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.  
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)  
tCLK  
t
CLKH  
tCLKL  
1
2
WCLK  
tDS  
tDH  
D0  
-
D17  
DATA IN VALID  
ENS  
tENH  
t
NO OPERATION  
WEN  
FF  
t
WFF  
tWFF  
(1)  
tSKEW1  
RCLK  
REN  
4294 drw 25  
NOTES:  
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising  
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.  
2. LD = HIGH.  
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.  
Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)  
FEBRUARY22,2006  
20  

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