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IDT72T20108L5BBI PDF预览

IDT72T20108L5BBI

更新时间: 2024-02-24 08:58:41
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片双倍数据速率
页数 文件大小 规格书
51页 478K
描述
2.5 VOLT HIGH-SPEED TeraSync? DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION

IDT72T20108L5BBI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
针数:208Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:3.6 ns
其他特性:ALTERNATIVE MEMORY WIDTH 10备用内存宽度:10
最大时钟频率 (fCLK):200 MHz周期时间:5 ns
JESD-30 代码:S-PBGA-B208JESD-609代码:e0
长度:17 mm内存密度:1310720 bit
内存集成电路类型:OTHER FIFO内存宽度:20
湿度敏感等级:3功能数量:1
端子数量:208字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX20可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA208,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:1.5/2.5,2.5 V
认证状态:Not Qualified座面最大高度:1.97 mm
最大待机电流:0.05 A子类别:FIFOs
最大压摆率:0.06 mA最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:17 mmBase Number Matches:1

IDT72T20108L5BBI 数据手册

 浏览型号IDT72T20108L5BBI的Datasheet PDF文件第2页浏览型号IDT72T20108L5BBI的Datasheet PDF文件第3页浏览型号IDT72T20108L5BBI的Datasheet PDF文件第4页浏览型号IDT72T20108L5BBI的Datasheet PDF文件第5页浏览型号IDT72T20108L5BBI的Datasheet PDF文件第6页浏览型号IDT72T20108L5BBI的Datasheet PDF文件第7页 
2.5VOLTHIGH-SPEEDTeraSyncDDR/SDRFIFO20-BIT/10-BITCONFIGURATION  
32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10  
131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10  
IDT72T2098, IDT72T20108  
IDT72T20118, IDT72T20128  
Programmable Almost-Empty and Almost-Full flags, each flag  
can default to one of four preselected offsets  
Dedicated serial clock input for serial programming of flag offsets  
User selectable input and output port bus sizing  
-x20 in to x20 out  
-x20 in to x10 out  
-x10 in to x20 out  
-x10 in to x10 out  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
FEATURES:  
Choose among the following memory organizations:  
IDT72T2098  
IDT72T20108  
IDT72T20118  
IDT72T20128  
32,768 x 20/65,536 x 10  
65,536 x 20/131,072 x 10  
131,072 x 20/262,144 x 10  
262,144 x 20/524,288 x 10  
Up to 250MHz Operation of Clocks  
-4ns read/write cycle time, 3.2ns access time  
Users selectable input port to output port data rates, 500Mb/s  
Data Rate  
Partial Reset clears data, but retains programmable settings  
Empty and Full flags signal FIFO status  
Select IDT Standard timing (using EF and FF flags) or First  
Word Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into High-Impedance state  
JTAG port, provided for Boundary Scan function  
208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch  
Easily expandable in depth and width  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
High-performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
-DDR to DDR  
-DDR to SDR  
-SDR to DDR  
-SDR to SDR  
User selectable HSTL or LVTTL I/Os  
Read Enable & Read Clock Echo outputs aid high speed operation  
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage  
3.3V Input tolerant  
Mark & Retransmit, resets read pointer to user marked position  
Write Chip Select (WCS) input enables/disables Write  
Operations  
Read Chip Select (RCS) synchronous to RCLK  
FUNCTIONALBLOCKDIAGRAM  
D0 -Dn (x20, x10)  
SREN SEN  
SCLK  
WCLK  
WSDR  
WEN  
WCS  
SI  
SO  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
WRITE CONTROL  
LOGIC  
FLAG  
LOGIC  
FWFT  
FSEL0  
FSEL1  
RAM ARRAY  
WRITE POINTER  
32,768 x 20 or 65,536 x 10  
65,536 x 20 or 131,072 x 10  
131,072 x 20 or 262,144 x 10  
262,144 x 20 or 524,288 x 10  
READ POINTER  
BUS  
IW  
OW  
CONFIGURATION  
RT  
READ  
CONTROL  
LOGIC  
MARK  
RSDR  
MRS  
PRS  
OUTPUT REGISTER  
RESET  
LOGIC  
TCK  
TRST  
TMS  
TDO  
JTAG CONTROL  
(BOUNDARY SCAN)  
RCLK  
REN  
RCS  
TDI  
Vref  
HSTL I/0  
CONTROL  
EREN  
OE  
5996 drw01  
HSTL  
Q0 -Qn (x20, x10)  
ERCLK  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheTeraSyncisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
DECEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5996/8  

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