5秒后页面跳转
IDT71V67703S80BQG PDF预览

IDT71V67703S80BQG

更新时间: 2024-02-19 02:42:13
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
23页 976K
描述
暂无描述

IDT71V67703S80BQG 数据手册

 浏览型号IDT71V67703S80BQG的Datasheet PDF文件第2页浏览型号IDT71V67703S80BQG的Datasheet PDF文件第3页浏览型号IDT71V67703S80BQG的Datasheet PDF文件第4页浏览型号IDT71V67703S80BQG的Datasheet PDF文件第5页浏览型号IDT71V67703S80BQG的Datasheet PDF文件第6页浏览型号IDT71V67703S80BQG的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
IDT71V67703  
IDT71V67903  
3.3V I/O, Burst Counter  
Flow-ThroughOutputs,SingleCycleDeselect  
Features  
data, address and control registers. There are no registers in the data  
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
theendofthewritecycle.  
256K x 36, 512K x 18 memory configurations  
Supports fast access times:  
– 7.5ns up to 117MHz clock frequency  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67703/7903canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandtheLBO inputpin.  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin thin plastic quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA).  
TheIDT71V67703/7903SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
Description  
The IDT71V67703/7903 are high-speed SRAMs organized as  
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
N/A  
5309 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V67903.  
DECEMBER 2003  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5309/05  

与IDT71V67703S80BQG相关器件

型号 品牌 描述 获取价格 数据表
IDT71V67703S80BQGI IDT Cache SRAM, 256KX36, 8ns, CMOS, PBGA165, 13 X 15 MM, GREEN, FBGA-165

获取价格

IDT71V67703S80BQI IDT 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs,

获取价格

IDT71V67703S80PF IDT 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs,

获取价格

IDT71V67703S80PF8 IDT Cache SRAM, 256KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, PLASTIC, TQFP-100

获取价格

IDT71V67703S80PFI IDT 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs,

获取价格

IDT71V67703S80PFI8 IDT Cache SRAM, 256KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, PLASTIC, TQFP-100

获取价格