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IDT71V2558S166PFG

更新时间： 2024-09-28 21:15:47
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
28页 1008K
描述
ZBT SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100

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中文翻译

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IDT71V2558S166PFG 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.84最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IDT71V2558S166PFG 数据手册

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128K x 36, 256K x 18  
IDT71V2556S  
IDT71V2558S  
IDT71V2556SA  
IDT71V2558SA  
3.3V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitread  
or write.  
The IDT71V2556/58 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V2556/58to  
besuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis  
initiated.  
TheIDT71V2556/58hasanon-chipburstcounter.Intheburstmode,  
theIDT71V2556/58canprovidefourcyclesofdataforasingleaddress  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
◆
128K x 36, 256K x 18 memory configurations  
◆
Supports high performance system speed - 200 MHz  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
◆
Single R/W (READ/WRITE) control pin  
◆
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
◆
◆
◆
◆
◆
complaint)  
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
TheIDT71V2556/58 are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles  
when turning the bus around between reads and writes, or writes and  
TM  
reads. Thus, they have been given the name ZBT , or Zero Bus  
Turnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Te s t Clo c k  
Te s t Data Outp ut  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
4875 tbl 01  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-4875/08  
1234567...28

中文翻译

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与IDT71V2558S166PFG相关器件

型号 品牌 获取价格 描述 数据表
IDT71V2558S166PFGI IDT

获取价格

 		ZBT SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2558S166PFI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S200BG IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S200BGI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S200BQ IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S200BQI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S200PF IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558S200PF8 IDT

获取价格

 		ZBT SRAM, 256KX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2558S200PF9 IDT

获取价格

 		ZBT SRAM, 256KX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2558S200PFI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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