Datasheet > IDT709349L7PFG

IDT709349L7PFG

更新时间： 2023-01-03 04:21:07

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	299K
描述
Dual-Port SRAM, 4KX18, 18ns, CMOS, PQFP100, TQFP-100

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中文翻译

获取价格

数据手册

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IDT709349L7PFG 数据手册

HIGH-SPEED 8/4K x 18

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

IDT709359/49L

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial:6.5/7.5/9ns(max.)

– Industrial: 7.5ns (max.)

Full synchronous operation on both ports

– 3.5ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

◆

Low-power operation

– IDT709359/49L

– 10ns cycle time, 100MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for 83 MHz

◆

Active:925mW(typ.)

Standby: 2.5mW (typ.)

◆

Flow-Through or Pipelined output mode on either Port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Available in a 100-pin Thin Quad Flatpack (TQFP) package

and a 100-pin fine pitch Ball Grid Array (fpBGA)

Functional Block Diagram

CE0L

CE1L

CE0R

CE1R

0/1

1b 0b

0a 1a

1a 0a

0b 1b

FT/PIPE

0/1

FT/PIPER

I/O9L-I/O17L

I/O0L-I/O8L

I/O9R-I/O17R

I/O0R-I/O8R

(1)

I/O

Control

I/O

Control

(1)

12L

A12R

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

C⁰L^RK

CLK

ADS

CNTEN

CNTRST

ADS

CNTEN

CNTRST

5633 drw 01

NOTE:

1. A12 is a NC for IDT709349.

AUGUST 2003

DSC-5633/2

12 3 4 5 6 7...16

中文翻译

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IDT709349L9BFI	IDT	获取价格	HIGH-SPEED 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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IDT709359_15	IDT	获取价格	HIGH-SPEED 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM