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IDT54823CLSOB PDF预览

IDT54823CLSOB

更新时间: 2024-02-11 00:46:21
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 90K
描述
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER

IDT54823CLSOB 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:28
Reach Compliance Code:unknown风险等级:5.84
其他特性:WITH CLEAR AND CLOCK ENABLE系列:FCT
JESD-30 代码:S-CQCC-N28JESD-609代码:e0
长度:11.4554 mm逻辑集成电路类型:BUS DRIVER
位数:9功能数量:1
端口数量:2端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified座面最大高度:2.54 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:11.4554 mmBase Number Matches:1

IDT54823CLSOB 数据手册

 浏览型号IDT54823CLSOB的Datasheet PDF文件第1页浏览型号IDT54823CLSOB的Datasheet PDF文件第3页浏览型号IDT54823CLSOB的Datasheet PDF文件第4页浏览型号IDT54823CLSOB的Datasheet PDF文件第5页浏览型号IDT54823CLSOB的Datasheet PDF文件第6页浏览型号IDT54823CLSOB的Datasheet PDF文件第7页 
IDT54/74FCT823A/B/C  
HIGH-PERFORMANCECMOSBUFFER  
MILITARYANDCOMMERCIAL TEMPERATURERANGES  
PINCONFIGURATION  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
2
OE  
D0  
VCC  
Y0  
INDEX  
D1  
D2  
Y1  
Y2  
3
4
4
3
2
28 27 26  
5
D2  
25  
24  
23  
22  
Y2  
1
6
D3  
D4  
NC  
D5  
D6  
D7  
Y3  
Y4  
D3  
D4  
D5  
Y3  
Y4  
Y5  
5
6
7
8
9
7
8
NC  
Y5  
9
21  
20  
19  
D6  
D7  
Y6  
Y7  
10  
Y6  
11  
Y7  
18  
12 13 14 15 16 17  
D8  
Y8  
10  
11  
CLR  
EN  
CP  
GND  
12  
CERDIP/ SOIC  
TOP VIEW  
LCC  
TOP VIEW  
LOGICSYMBOL  
ABSOLUTEMAXIMUMRATINGS(1)  
9
Symbol Rating  
Commercial  
Military  
Unit  
D
D
9
(2)  
Q
Y
VTERM  
Terminal Voltage  
–0.5 to +7  
–0.5 to +7  
V
with Respect to GND  
Terminal Voltage  
CP EN CLR  
(3)  
VTERM  
–0.5 to VCC –0.5 to VCC  
V
CP  
EN  
CLR  
with Respect to GND  
Operating Temperature  
Temperature under BIAS  
Storage Temperature  
Power Dissipation  
TA  
0 to +70 –55 to +125  
°C  
°C  
°C  
W
TBIAS  
TSTG  
PT  
–55 to +125 –65 to +135  
–55 to +125 –65 to +150  
OE  
0.5  
0.5  
PINDESCRIPTION  
IOUT  
DC Output Current  
120  
120  
mA  
Pin Name  
Dx  
I/O  
Description  
D flip-flop data inputs  
NOTES:  
I
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability. No terminal voltage may exceed  
Vcc by +0.5V unless otherwise noted.  
CLR  
For both inverting and non-inverting registers, when  
the clear input is LOW and OE is LOW, the Qx  
outputs are LOW. When the clear input is HIGH, data  
can be entered into the register.  
2. Input and Vcc terminals only.  
3. Output and I/O terminals only.  
CP  
I
Clock Pulse for the Register; enters data into the  
register on the LOW-to-HIGH transition.  
Y x  
O
I
Register 3-state outputs  
EN  
Clock Enable. When the clock enable is LOW, data  
on the DI input is transferred to the QI output on the  
LOW-to-HIGH clock transition. When the clock enable  
is HIGH, the QI outputs do not change state,  
regardless of the data or clock input transitions.  
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter(1)  
Input Capacitance  
Output Capacitance  
Conditions  
Typ.  
Max. Unit  
CIN  
VIN = 0V  
6
8
10  
12  
pF  
pF  
COUT  
VOUT = 0V  
OE  
I
Output Control. When the OE input is HIGH, the Yx  
outputs are in the high impedance state. When the OE  
input is LOW, the TRUE register data is present at the  
Yx outputs.  
NOTE:  
1. This parameter is measured at characterization but not tested.  
2

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