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ICS9FG108CGLF PDF预览

ICS9FG108CGLF

更新时间: 2024-01-03 04:17:37
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
19页 252K
描述
Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM WIDTH, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48

ICS9FG108CGLF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:6.10 MM WIDTH, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.76JESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:12.5 mm
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:400 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:25 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

ICS9FG108CGLF 数据手册

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DATASHEET  
ICS9FG108  
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
Description  
Features/Benefits  
ICS9FG108 is a Frequency Timing Generator that provides 8  
differential output pairs that are compliant to the Intel CK410  
specification. It also provides support for PCI-Express, next  
generation I/O, and SATA. The part synthesizes several output  
frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal.  
The device can also be driven by a reference input clock instead of  
a crystal. It provides outputs with cycle-to-cycle jitter of less than 50  
ps and output-to-output skew of less than 65 ps. ICS9FG108 also  
provides a copy of the reference clock. Frequency selection can be  
accomplished via strap pins or SMBus control.  
Generates common frequencies from 14.318 MHz or  
25 MHz  
Crystal or reference input  
8 - 0.7V current-mode differential output pairs  
Supports Serial-ATA at 100 MHz  
Two spread spectrum modes: 0 to -0.5 downspread  
and +/-0.25% centerspread  
Unused inputs may be disabled in either driven or Hi-Z  
state for power management.  
Key Specifications  
Programmable OE Polarity  
M/N Programming  
Output cycle-to-cycle jitter < 50 ps  
Output to output skew < 65 ps  
+/-300 ppm frequency accuracy on output clocks  
+/-150 ppm frequency accuracy @100 MHz outputs  
48-pin SSOP/TSSOP package  
Available in RoHS compliant packaging  
Funtional Block Diagram  
XIN/CLKIN  
X2  
R EFOUT  
OSC  
OE(7:0)  
8
STOP  
LOGIC  
PROGRAMMABLE  
SPREAD PLL  
DIF(7:0)  
SPREAD  
SEL14M_25M#  
DIF_STOP#  
FS(2:0)  
CONTROL  
LOGIC  
SDATA  
SCLK  
IREF  
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA  
ICS9FG108 REV G 04/06/07  
1

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