PRELIMINARY
ICS8MX4
Integrated
Circuit
Systems, Inc.
LVDS CLOCK OSCILLATOR
ICS8MX4
LOW JITTER, HIGH FREQUENCY XTAL OSCILLATOR
• Stable, ultra low jitter, LVDS clock generation
• For Gigabit Ethernet, Fibre Channel, PCI-Express™, other applications
• Clock output frequencies from 7ꢀMHz to 7ꢀ0MHz
• One differential LVDS clock output
• Output Enable (OE) pin (high impedance – when low)
• Small 6-pin ꢀmm x 7mm x 1.ꢀmm SMT ceramic package
• Low profile package allows back-side PCB mounting
• Pb-free RoHS compliant (by default; no additional code required)
• 3.3V or 2.ꢀV device power supply options
8Mx4
(Top View )
O
O
• Commercial (0 to +70 C) and Industrial (-40 to +8ꢀ C) temperatures
• Frequency stability of ꢀ0ppm or 100ppm
(including initial accuracy, operating temperature variation, supply voltage
variation, load variation, reflow drift, and aging for 10 years)
• Low phase jitter < 1 ps rms maximum (12kHz to 20MHz)
6-pin CERHERMETIC 5mm x 7mm x 1.5mm SMT
ELECTRICAL SPECIFICATIONS
Unless stated otherwise, VDD = 3.3V ꢀ5 or 2.ꢀV ꢀ5, TA = 0°C to +70°C (commercial), TA = -40°C to +80°C (industrial)
Specifications
Min.
Typ.
Max.
Units
Item
Symbol
Test Conditions
DC Characteristics
Power Supply
(VDD, GND pins)
3.13ꢀ
2.37ꢀ
3.3
2.ꢀ
83
3.46ꢀ
2.62ꢀ
V
V
3.3V operation
Power Supply Voltage
VDD
2.ꢀV operation (8MJ4 and 8MK4 only)
Power Supply Current
Current w/Output Disabled
Input Capacitance
IDD
mA
mA
pF
V
OE = VDD
IOED
CIN
VIH
<0.6
OE = GND
4
Output Enable
(OE pin)
LVCMOS/LVTTL
Input High Voltage
0.7 * VDD
-1ꢀ0
Input Low Voltage
VIL
0.3 * VDD
ꢀ
V
Input High Current
IIH
µA
µA
VDD = VIN = 3.46ꢀV or 2.62ꢀV
Input Low Current
IIL
VDD = 3.46ꢀV or 2.62ꢀV, VIN = 0V
Internal Pullup Resistor
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
RPULLUP
VOD
VOD
VOS
ꢀ1
kΩ
Clock Output
Level
(OUT, nOUT)
LVDS
3ꢀ0
mV
mV
V
Δ
ꢀ0
100
Ω termination between OUT and nOUT.
See Parameter Measurement Information.
1.2ꢀ
VOS Magnitude Change
Δ
VOS
1ꢀ0
mV
AC Characteristics
Output
(OUT, nOUT)
Output Frequency Range
7ꢀ
7ꢀ0
100
ꢀ0
MHz
All conditions
ppm p-p 8MH4 & 8MK4
ppm p-p 8MG4 & 8MJ4
5
Includes frequency set, VDD, TA and
load variation, reflow drift, 10 yr. aging
Frequency Stability Error
Δ
f/fO
Output Duty Cycle
Output Rise Time
Output Fall Time
odc
tR
ꢀ0
See Output Duty Cycle Diagram
and Rise/Fall Time Diagram in
Parameter Measurement Information
600
600
10
ps
ps
205 to 805
of VOD
tF
Oscillator Start-up Time
RMS Phase Jitter, Random1 t jit (Ø)
tOSC
ms
Time at Min. VDD (3.13ꢀV or 2.37ꢀV) to be 0s
design target
<1
ps rms
ps
2
Jitter
tDS
tRS
0.2
3
Deterministic
2
ps
ps
ps
ps
Random, σ of random jitter
2
tRMS
3
Root Mean Square,
Peak-to-Peak
σ of total jitter distribution
2
tP-P
2ꢀ
4
2
tacc
Accumulated Jitter, n = 2 to ꢀ0,000 cycles
NOTE 1: Measured using an Aeroflex PN9ꢀ00 with a 12kHz to 20MHz integration range. NOTE 2: Measured using a Wavecrest SIA-3000.
Supply Voltage & Frequency Accuracy
G =
H =
J =
3.3V / 3.3V
3.3V / 3.3V
2.ꢀV / 3.3V
2.ꢀV / 3.3V
ꢀ0 ppm
100 ppm
ꢀ0 ppm
The Preliminary Information presented herein represents a product in prototyping or pre-production. The
noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorpo-
rated (ICS) reserves the right to change any circuitry or specifications without notice.
K =
100 ppm
8Mx4AJ
www.icst.com/products/hiperclocks.html
REV.B FEBRUARY 10, 2006
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