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ICS889875AKT PDF预览

ICS889875AKT

更新时间: 2024-09-30 14:33:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
15页 1123K
描述
Low Skew Clock Driver, 889875 Series, 2 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16

ICS889875AKT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:VQCCN, LCC16,.12SQ,20针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.9系列:889875
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N16
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:16
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:VQCCN封装等效代码:LCC16,.12SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):225电源:2.5 V
Prop。Delay @ Nom-Sup:1.14 ns传播延迟(tpd):1.14 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.015 ns
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

ICS889875AKT 数据手册

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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER  
W/INTERNAL TERMINATION  
ICS889875  
General Description  
Features  
The ICS889875 is a high speed Differential-to-  
Two LVDS outputs  
S
IC  
LVDS Buffer/Divider w/Internal Termination and is a  
member of the HiPerClockS™ family of high  
performance clock solutions from IDT. The  
ICS889875 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16  
Frequency divide select options: ÷1, ÷2, ÷4, ÷8, ÷16  
HiPerClockS™  
IN, nIN input can accept the following differential input levels:  
LVPECL, LVDS, CML  
Output frequency: >2GHz  
output dividers. The clock input has internal termination resistors,  
allowing it to interface with several differential signal types while  
minimizing the number of required external components. The  
device is packaged in a small, 3mm x 3mm VFQFN package,  
making it ideal for use on space-constrained boards.  
Cycle-to-cycle jitter: 1ps RMS (maximum)  
Total jitter: 10ps (typical)  
Output skew: 15ps (maximum)  
Part-to-part skew: 280ps (maximum)  
Propagation Delay: 1140ps (maximum)  
Full 2.5V supply mode  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignment  
Block Diagram  
Pullup  
S2  
16 15 14 13  
1
2
3
Q0  
nQ0  
Q1  
12  
11  
10  
IN  
nRESET/  
nDISABLE  
VT  
Enable  
FF  
Pullup  
VREF_AC  
nIN  
nQ1  
4
9
5
6
7
8
Enable  
MUX  
VREF_AC  
Q0  
nQ0  
MUX  
ICS889875  
IN  
VT  
Q1  
50  
50Ω  
÷2, ÷4,  
÷8, ÷16  
16-Lead VFQFN  
3mm x 3mm x 0.925mm package body  
nQ1  
nIN  
K Package  
Top View  
Pullup  
Pullup  
S1  
S0  
Decoder  
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION  
1
ICS889875AK REV. A FEBRUARY 13, 2008  

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